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Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Yann Gautier66386952018-07-05 16:49:51 +02006#include <dt-bindings/pinctrl/stm32-pinfunc.h>
Yann Gautier7b7e4bf2019-01-17 19:16:03 +01007
Yann Gautier66386952018-07-05 16:49:51 +02008/ {
9 soc {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010010 pinctrl: pin-controller@50002000 {
Yann Gautier66386952018-07-05 16:49:51 +020011 #address-cells = <1>;
12 #size-cells = <1>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010013 compatible = "st,stm32mp157-pinctrl";
Yann Gautier66386952018-07-05 16:49:51 +020014 ranges = <0 0x50002000 0xa400>;
15 pins-are-numbered;
16
17 gpioa: gpio@50002000 {
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
22 reg = <0x0 0x400>;
23 clocks = <&rcc GPIOA>;
24 st,bank-name = "GPIOA";
25 status = "disabled";
26 };
27
28 gpiob: gpio@50003000 {
29 gpio-controller;
30 #gpio-cells = <2>;
31 interrupt-controller;
32 #interrupt-cells = <2>;
33 reg = <0x1000 0x400>;
34 clocks = <&rcc GPIOB>;
35 st,bank-name = "GPIOB";
36 status = "disabled";
37 };
38
39 gpioc: gpio@50004000 {
40 gpio-controller;
41 #gpio-cells = <2>;
42 interrupt-controller;
43 #interrupt-cells = <2>;
44 reg = <0x2000 0x400>;
45 clocks = <&rcc GPIOC>;
46 st,bank-name = "GPIOC";
47 status = "disabled";
48 };
49
50 gpiod: gpio@50005000 {
51 gpio-controller;
52 #gpio-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 reg = <0x3000 0x400>;
56 clocks = <&rcc GPIOD>;
57 st,bank-name = "GPIOD";
58 status = "disabled";
59 };
60
61 gpioe: gpio@50006000 {
62 gpio-controller;
63 #gpio-cells = <2>;
64 interrupt-controller;
65 #interrupt-cells = <2>;
66 reg = <0x4000 0x400>;
67 clocks = <&rcc GPIOE>;
68 st,bank-name = "GPIOE";
69 status = "disabled";
70 };
71
72 gpiof: gpio@50007000 {
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 reg = <0x5000 0x400>;
78 clocks = <&rcc GPIOF>;
79 st,bank-name = "GPIOF";
80 status = "disabled";
81 };
82
83 gpiog: gpio@50008000 {
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
88 reg = <0x6000 0x400>;
89 clocks = <&rcc GPIOG>;
90 st,bank-name = "GPIOG";
91 status = "disabled";
92 };
93
94 gpioh: gpio@50009000 {
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 reg = <0x7000 0x400>;
100 clocks = <&rcc GPIOH>;
101 st,bank-name = "GPIOH";
102 status = "disabled";
103 };
104
105 gpioi: gpio@5000a000 {
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 reg = <0x8000 0x400>;
111 clocks = <&rcc GPIOI>;
112 st,bank-name = "GPIOI";
113 status = "disabled";
114 };
115
116 gpioj: gpio@5000b000 {
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 reg = <0x9000 0x400>;
122 clocks = <&rcc GPIOJ>;
123 st,bank-name = "GPIOJ";
124 status = "disabled";
125 };
126
127 gpiok: gpio@5000c000 {
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0xa000 0x400>;
133 clocks = <&rcc GPIOK>;
134 st,bank-name = "GPIOK";
135 status = "disabled";
136 };
137
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100138 qspi_bk1_pins_a: qspi-bk1-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200139 pins1 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100140 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
141 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
142 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
143 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
Yann Gautier66386952018-07-05 16:49:51 +0200144 bias-disable;
145 drive-push-pull;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100146 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200147 };
148 pins2 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100149 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
150 bias-pull-up;
151 drive-push-pull;
152 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200153 };
154 };
155
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100156 qspi_bk2_pins_a: qspi-bk2-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200157 pins1 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100158 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
159 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
160 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
161 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
Yann Gautier66386952018-07-05 16:49:51 +0200162 bias-disable;
163 drive-push-pull;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100164 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200165 };
166 pins2 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100167 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
168 bias-pull-up;
169 drive-push-pull;
170 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200171 };
172 };
173
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100174 qspi_clk_pins_a: qspi-clk-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200175 pins {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100176 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
177 bias-disable;
178 drive-push-pull;
179 slew-rate = <3>;
180 };
181 };
182
183 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
184 pins1 {
Yann Gautier66386952018-07-05 16:49:51 +0200185 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
186 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
187 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
188 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
Yann Gautier66386952018-07-05 16:49:51 +0200189 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100190 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200191 drive-push-pull;
192 bias-disable;
193 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100194 pins2 {
195 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
196 slew-rate = <2>;
197 drive-push-pull;
198 bias-disable;
199 };
Yann Gautier66386952018-07-05 16:49:51 +0200200 };
201
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100202 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200203 pins1 {
204 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
205 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
206 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100207 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200208 drive-push-pull;
209 bias-pull-up;
210 };
211 pins2{
212 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
213 bias-pull-up;
214 };
215 };
216
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100217 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
218 pins1 {
219 pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */
220 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
221 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
222 slew-rate = <3>;
223 drive-push-pull;
224 bias-pull-up;
225 };
226 pins2 {
227 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
228 bias-pull-up;
229 };
230 };
231
232 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
233 pins1 {
Yann Gautier66386952018-07-05 16:49:51 +0200234 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
235 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
236 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
237 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
Yann Gautier66386952018-07-05 16:49:51 +0200238 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100239 slew-rate = <1>;
240 drive-push-pull;
241 bias-pull-up;
242 };
243 pins2 {
244 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
245 slew-rate = <2>;
Yann Gautier66386952018-07-05 16:49:51 +0200246 drive-push-pull;
247 bias-pull-up;
248 };
249 };
250
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100251 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200252 pins {
253 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
254 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
255 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
256 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100257 slew-rate = <1>;
Yann Gautier66386952018-07-05 16:49:51 +0200258 drive-push-pull;
259 bias-pull-up;
260 };
261 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100262
263 uart4_pins_a: uart4-0 {
264 pins1 {
265 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
266 bias-disable;
267 drive-push-pull;
268 slew-rate = <0>;
269 };
270 pins2 {
271 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
272 bias-disable;
273 };
274 };
275
276 usart3_pins_a: usart3-0 {
277 pins1 {
278 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
279 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
280 bias-disable;
281 drive-push-pull;
282 slew-rate = <0>;
283 };
284 pins2 {
285 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
286 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
287 bias-disable;
288 };
289 };
Yann Gautier66386952018-07-05 16:49:51 +0200290 };
291
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100292 pinctrl_z: pin-controller-z@54004000 {
Yann Gautier66386952018-07-05 16:49:51 +0200293 #address-cells = <1>;
294 #size-cells = <1>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100295 compatible = "st,stm32mp157-z-pinctrl";
Yann Gautier66386952018-07-05 16:49:51 +0200296 ranges = <0 0x54004000 0x400>;
297 pins-are-numbered;
298
299 gpioz: gpio@54004000 {
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 reg = <0 0x400>;
305 clocks = <&rcc GPIOZ>;
306 st,bank-name = "GPIOZ";
307 st,bank-ioport = <11>;
308 status = "disabled";
309 };
310
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100311 i2c4_pins_a: i2c4-0 {
Yann Gautier66386952018-07-05 16:49:51 +0200312 pins {
313 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
314 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
315 bias-disable;
316 drive-open-drain;
317 slew-rate = <0>;
318 };
319 };
320 };
321 };
322};