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git01.mediatek.com / filogic / atf / 779fd46916fceddf0085a21ed5f1c602642d2550 / . / plat / marvell / armada / a8k / a80x0 / board / phy-porting-layer.h
blob: abd85b5d254e3356b1abc63c916a888eb6cedf31 [file] [log] [blame]
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef PHY_PORTING_LAYER_H
9#define PHY_PORTING_LAYER_H
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]10
11#define MAX_LANE_NR 6
12
13static const struct xfi_params
14 xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
15 /* AP0 */
16 {
17 /* CP 0 */
18 {
19 { 0 }, /* Comphy0 */
20 { 0 }, /* Comphy1 */
21 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
22 .align90 = 0x5f,
23 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
24 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
25 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
26 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
27 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
28 .valid = 0x1 }, /* Comphy2 */
29 { 0 }, /* Comphy3 */
Konstantin Porotchkin93f1e432018-10-21 16:48:33 +0300[diff] [blame]30 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
31 .align90 = 0x5f,
32 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
33 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
34 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
35 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
36 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
37 .valid = 0x1 }, /* Comphy4 */
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]38 { 0 }, /* Comphy5 */
39 },
40
41 /* CP 1 */
42 {
43 { 0 }, /* Comphy0 */
44 { 0 }, /* Comphy1 */
45 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
46 .align90 = 0x5f,
47 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
48 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
49 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
50 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
51 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
52 .valid = 0x1 }, /* Comphy2 */
53 { 0 }, /* Comphy3 */
Konstantin Porotchkin93f1e432018-10-21 16:48:33 +0300[diff] [blame]54 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
55 .align90 = 0x5f,
56 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
57 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
58 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
59 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
60 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
61 .valid = 0x1 }, /* Comphy4 */
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]62 { 0 }, /* Comphy5 */
63 },
64 },
65};
66
67static const struct sata_params
68 sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
69 /* AP0 */
70 {
71 /* CP 0 */
72 {
73 { 0 }, /* Comphy0 */
74 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
75 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
76 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
77 .g3_emph_en = 0x1,
78 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
79 .g3_tx_amp_adj = 0x1,
80 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
81 .g3_tx_emph_en = 0x0,
82 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
83 .g3_tx_emph = 0x1,
84 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
85 .g3_ffe_cap_sel = 0xf,
86 .align90 = 0x61,
87 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
88 .g3_rx_selmuff = 0x3,
89 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
90 .g3_rx_selmufi = 0x3,
91 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
92 .g3_rx_selmupf = 0x2,
93 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
94 .g3_rx_selmupi = 0x2,
95 .valid = 0x1
96 }, /* Comphy1 */
97 { 0 }, /* Comphy2 */
98 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
99 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
100 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
101 .g3_emph_en = 0x1,
102 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
103 .g3_tx_amp_adj = 0x1,
104 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
105 .g3_tx_emph_en = 0x0,
106 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
107 .g3_tx_emph = 0x1,
108 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
109 .g3_ffe_cap_sel = 0xf,
110 .align90 = 0x61,
111 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
112 .g3_rx_selmuff = 0x3,
113 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
114 .g3_rx_selmufi = 0x3,
115 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
116 .g3_rx_selmupf = 0x2,
117 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
118 .g3_rx_selmupi = 0x2,
119 .valid = 0x1
120 }, /* Comphy3 */
121 { 0 }, /* Comphy4 */
122 { 0 }, /* Comphy5 */
123 },
124
125 /* CP 1 */
126 {
127 { 0 }, /* Comphy0 */
128 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
129 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
130 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
131 .g3_emph_en = 0x1,
132 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
133 .g3_tx_amp_adj = 0x1,
134 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
135 .g3_tx_emph_en = 0x0,
136 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
137 .g3_tx_emph = 0x1,
138 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
139 .g3_ffe_cap_sel = 0xf,
140 .align90 = 0x61,
141 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
142 .g3_rx_selmuff = 0x3,
143 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
144 .g3_rx_selmufi = 0x3,
145 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
146 .g3_rx_selmupf = 0x2,
147 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
148 .g3_rx_selmupi = 0x2,
149 .valid = 0x1
150 }, /* Comphy1 */
151 { 0 }, /* Comphy2 */
152 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
153 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
154 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
155 .g3_emph_en = 0x1,
156 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
157 .g3_tx_amp_adj = 0x1,
158 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
159 .g3_tx_emph_en = 0x0,
160 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
161 .g3_tx_emph = 0x1,
162 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
163 .g3_ffe_cap_sel = 0xf,
164 .align90 = 0x61,
165 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
166 .g3_rx_selmuff = 0x3,
167 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
168 .g3_rx_selmufi = 0x3,
169 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
170 .g3_rx_selmupf = 0x2,
171 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
172 .g3_rx_selmupi = 0x2,
173 .valid = 0x1
174 }, /* Comphy3 */
175 { 0 }, /* Comphy4 */
176 { 0 }, /* Comphy5 */
177
178 },
179 },
180};
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]181#endif /* PHY_PORTING_LAYER_H */