blob: 52c04cd966c5796bb45932cc563e8a47027a4aa6 [file] [log] [blame]
Manoj Kumar779e4152020-07-31 12:32:36 +01001/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10 compatible = "arm,morello";
11
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 serial0 = &soc_uart0;
18 };
19
20 gic: interrupt-controller@2c010000 {
21 compatible = "arm,gic-600", "arm,gic-v3";
22 #address-cells = <2>;
23 #interrupt-cells = <3>;
24 #size-cells = <2>;
25 ranges;
26 interrupt-controller;
27 };
28
29 pmu {
30 compatible = "arm,armv8-pmuv3";
31 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
32 };
33
34 spe-pmu {
35 compatible = "arm,statistical-profiling-extension-v1";
36 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
37 };
38
39 psci {
40 compatible = "arm,psci-0.2";
41 method = "smc";
42 };
43
44 timer {
45 compatible = "arm,armv8-timer";
46 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
47 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
48 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
49 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
50 };
51
52 mailbox: mhu@45000000 {
53 compatible = "arm,mhu-doorbell", "arm,primecell";
54 reg = <0x0 0x45000000 0x0 0x1000>;
55 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-names = "mhu_lpri_rx",
58 "mhu_hpri_rx";
59 #mbox-cells = <2>;
60 mbox-name = "ARM-MHU";
61 clocks = <&soc_refclk100mhz>;
62 clock-names = "apb_pclk";
63 };
64
65 sram: sram@45200000 {
66 compatible = "mmio-sram";
67 reg = <0x0 0x45200000 0x0 0x8000>;
68
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 0x0 0x45200000 0x8000>;
72
73 cpu_scp_hpri0: scp-shmem@0 {
74 compatible = "arm,scmi-shmem";
75 reg = <0x0 0x80>;
76 };
77
78 cpu_scp_hpri1: scp-shmem@80 {
79 compatible = "arm,scmi-shmem";
80 reg = <0x80 0x80>;
81 };
82 };
83
84 soc_refclk100mhz: refclk100mhz {
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <100000000>;
88 clock-output-names = "apb_pclk";
89 };
90
91 soc_uartclk: uartclk {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <50000000>;
95 clock-output-names = "uartclk";
96 };
97
98 soc_uart0: uart@2a400000 {
99 compatible = "arm,pl011", "arm,primecell";
100 reg = <0x0 0x2a400000 0x0 0x1000>;
101 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
103 clock-names = "uartclk", "apb_pclk";
104 status = "okay";
105 };
106};