Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 1 | /* |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Arm Limited. All rights reserved. |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 8 | |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 9 | /dts-v1/; |
| 10 | |
| 11 | / { |
| 12 | model = "V2F-1XV7 Cortex-A7x1 SMM"; |
| 13 | compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress"; |
| 14 | interrupt-parent = <&gic>; |
| 15 | #address-cells = <2>; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 16 | #size-cells = <1>; |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 17 | |
| 18 | cpus { |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 19 | #address-cells = <1>; |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 20 | #size-cells = <0>; |
| 21 | |
| 22 | cpu@0 { |
| 23 | device_type = "cpu"; |
| 24 | compatible = "arm,cortex-a7"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 25 | reg = <0>; |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 26 | }; |
| 27 | }; |
| 28 | |
| 29 | memory@0,80000000 { |
| 30 | device_type = "memory"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 31 | reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */ |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | gic: interrupt-controller@2c001000 { |
| 35 | compatible = "arm,cortex-a15-gic"; |
| 36 | #interrupt-cells = <3>; |
| 37 | #address-cells = <0>; |
| 38 | interrupt-controller; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 39 | reg = <0 0x2c001000 0x1000>, |
| 40 | <0 0x2c002000 0x1000>, |
| 41 | <0 0x2c004000 0x2000>, |
| 42 | <0 0x2c006000 0x2000>; |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 43 | interrupts = <1 9 0xf04>; |
| 44 | }; |
| 45 | |
| 46 | smbclk: refclk24mhzx2 { |
| 47 | /* Reference 24MHz clock x 2 */ |
| 48 | compatible = "fixed-clock"; |
| 49 | #clock-cells = <0>; |
| 50 | clock-frequency = <48000000>; |
| 51 | clock-output-names = "smclk"; |
| 52 | }; |
| 53 | |
| 54 | smb { |
| 55 | compatible = "simple-bus"; |
| 56 | |
| 57 | #address-cells = <2>; |
| 58 | #size-cells = <1>; |
| 59 | ranges = <0 0 0 0x08000000 0x04000000>, |
| 60 | <1 0 0 0x14000000 0x04000000>, |
| 61 | <2 0 0 0x18000000 0x04000000>, |
| 62 | <3 0 0 0x1c000000 0x04000000>, |
| 63 | <4 0 0 0x0c000000 0x04000000>, |
| 64 | <5 0 0 0x10000000 0x04000000>; |
| 65 | |
| 66 | #interrupt-cells = <1>; |
| 67 | interrupt-map-mask = <0 0 63>; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame] | 68 | interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 84 | <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| 85 | <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| 86 | <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 87 | |
Andre Przywara | 774e64a | 2022-08-19 10:45:17 +0100 | [diff] [blame^] | 88 | #include "rtsm_ve-motherboard.dtsi" |
Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame] | 89 | }; |
| 90 | }; |