| developer | 2e25992 | 2024-12-27 19:38:01 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2025, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MCUCFG_H |
| 8 | #define MCUCFG_H |
| 9 | |
| 10 | #ifndef __ASSEMBLER__ |
| 11 | #include <stdint.h> |
| 12 | #endif /*__ASSEMBLER__*/ |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000) |
| 16 | |
| 17 | /* CPC related registers */ |
| 18 | #define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004) |
| 19 | #define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010) |
| 20 | #define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014) |
| 21 | #define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104) |
| 22 | #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114) |
| 23 | #define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118) |
| 24 | #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c) |
| 25 | #define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124) |
| 26 | #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128) |
| 27 | #define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140) |
| 28 | #define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144) |
| 29 | #define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c) |
| 30 | #define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8) |
| 31 | #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac) |
| 32 | #define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200) |
| 33 | #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204) |
| 34 | #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208) |
| 35 | #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c) |
| 36 | #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210) |
| 37 | #define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214) |
| 38 | #define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220) |
| 39 | #define CPC_CPU0_LATENCY (MCUSYS_CPC_BASE + 0x240) |
| 40 | #define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x260) |
| 41 | #define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x264) |
| 42 | #define CPC_MCUSYS_LATENCY (MCUSYS_CPC_BASE + 0x268) |
| 43 | #define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x270) |
| 44 | #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274) |
| 45 | #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) |
| 46 | |
| 47 | #define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x280) |
| 48 | #define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x284) |
| 49 | #define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x288) |
| 50 | #define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x28c) |
| 51 | #define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x290) |
| 52 | |
| 53 | /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */ |
| 54 | #define CPC_CTRL_ENABLE BIT(16) |
| 55 | #define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */ |
| 56 | #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) |
| 57 | |
| 58 | #define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17) |
| 59 | #define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20) |
| 60 | |
| 61 | #define CPC_CORE_FSM_ON BIT(3) |
| 62 | |
| 63 | #define CPC_WAKEUP_STAT_NONE 0x0 |
| 64 | |
| 65 | /* Define SPMC_CONTROL_CONFIG */ |
| 66 | #define SPMC_CONTROL_CONFIG (MCUCFG_BASE + 0x480) |
| 67 | |
| 68 | /* bit fields of SPMC_CONTROL_CONFIG */ |
| 69 | #define SPMC_CPU_PWR_ON_REQ BIT(0) |
| 70 | #define SPMC_CPUTOP_PWR_ON_REQ BIT(8) |
| 71 | #define SPMC_MCUSYS_PWR_ON_REQ BIT(9) |
| 72 | #define SPMC_CPU_RESET_PWRON_CONFIG BIT(16) |
| 73 | #define SPMC_CPUTOP_RESET_PWRON_CONFIG BIT(24) |
| 74 | #define SPMC_MCUSYS_RESET_PWRON_CONFIG BIT(25) |
| 75 | |
| 76 | #endif /* __MCUCFG_H__ */ |