Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. |
Michal Simek | 7dd8d72 | 2023-02-20 13:01:27 +0100 | [diff] [blame] | 3 | * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 9 | #include <errno.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <bl31/bl31.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Venkatesh Yadav Abbarapu | 34fbf1f | 2020-11-27 04:45:01 -0700 | [diff] [blame] | 14 | #include <drivers/arm/dcc.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <drivers/console.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 16 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <plat/common/platform.h> |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 18 | #include <lib/mmio.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 20 | #include <custom_svc.h> |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 21 | #include <plat_startup.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 22 | #include <plat_private.h> |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 23 | #include <zynqmp_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 24 | |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 25 | #include <common/fdt_fixup.h> |
| 26 | #include <common/fdt_wrappers.h> |
| 27 | #include <libfdt.h> |
| 28 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 29 | static entry_point_info_t bl32_image_ep_info; |
| 30 | static entry_point_info_t bl33_image_ep_info; |
| 31 | |
| 32 | /* |
| 33 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 34 | * the security state specified. BL33 corresponds to the non-secure image type |
| 35 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 36 | * if the image does not exist. |
| 37 | */ |
Venkatesh Yadav Abbarapu | c70726f | 2022-05-16 17:44:33 +0530 | [diff] [blame] | 38 | struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 39 | { |
Venkatesh Yadav Abbarapu | c70726f | 2022-05-16 17:44:33 +0530 | [diff] [blame] | 40 | entry_point_info_t *next_image_info; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 41 | |
Venkatesh Yadav Abbarapu | c70726f | 2022-05-16 17:44:33 +0530 | [diff] [blame] | 42 | assert(sec_state_is_valid(type)); |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 43 | if (type == NON_SECURE) { |
Venkatesh Yadav Abbarapu | c70726f | 2022-05-16 17:44:33 +0530 | [diff] [blame] | 44 | next_image_info = &bl33_image_ep_info; |
| 45 | } else { |
| 46 | next_image_info = &bl32_image_ep_info; |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 47 | } |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 48 | |
Venkatesh Yadav Abbarapu | c70726f | 2022-05-16 17:44:33 +0530 | [diff] [blame] | 49 | return next_image_info; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | /* |
Alistair Francis | b8d474f | 2017-11-30 16:21:21 -0800 | [diff] [blame] | 53 | * Set the build time defaults. We want to do this when doing a JTAG boot |
| 54 | * or if we can't find any other config data. |
| 55 | */ |
| 56 | static inline void bl31_set_default_config(void) |
| 57 | { |
| 58 | bl32_image_ep_info.pc = BL32_BASE; |
| 59 | bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); |
| 60 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
| 61 | bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, |
| 62 | DISABLE_ALL_EXCEPTIONS); |
| 63 | } |
| 64 | |
| 65 | /* |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 66 | * Perform any BL31 specific platform actions. Here is an opportunity to copy |
John Tsichritzis | d653d33 | 2018-09-14 10:34:57 +0100 | [diff] [blame] | 67 | * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 68 | * are lost (potentially). This needs to be done before the MMU is initialized |
| 69 | * so that the memory layout can be used while creating page tables. |
| 70 | */ |
Antonio Nino Diaz | 012c8bf | 2018-09-24 17:16:52 +0100 | [diff] [blame] | 71 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 72 | u_register_t arg2, u_register_t arg3) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 73 | { |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 74 | uint64_t atf_handoff_addr; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 75 | |
Venkatesh Yadav Abbarapu | 0bd80de | 2021-12-19 21:32:00 -0700 | [diff] [blame] | 76 | if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) { |
Venkatesh Yadav Abbarapu | 34fbf1f | 2020-11-27 04:45:01 -0700 | [diff] [blame] | 77 | /* Register the console to provide early debug support */ |
| 78 | static console_t bl31_boot_console; |
| 79 | (void)console_cdns_register(ZYNQMP_UART_BASE, |
| 80 | zynqmp_get_uart_clk(), |
| 81 | ZYNQMP_UART_BAUDRATE, |
| 82 | &bl31_boot_console); |
| 83 | console_set_scope(&bl31_boot_console, |
| 84 | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); |
| 85 | } else if (ZYNQMP_CONSOLE_IS(dcc)) { |
| 86 | /* Initialize the dcc console for debug */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 87 | int32_t rc = console_dcc_register(); |
Venkatesh Yadav Abbarapu | 34fbf1f | 2020-11-27 04:45:01 -0700 | [diff] [blame] | 88 | if (rc == 0) { |
| 89 | panic(); |
| 90 | } |
Venkatesh Yadav Abbarapu | ccf6da7 | 2022-05-04 14:23:32 +0530 | [diff] [blame] | 91 | } else { |
| 92 | ERROR("BL31: No console device found.\n"); |
Venkatesh Yadav Abbarapu | 34fbf1f | 2020-11-27 04:45:01 -0700 | [diff] [blame] | 93 | } |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 94 | /* Initialize the platform config for future decision making */ |
| 95 | zynqmp_config_setup(); |
| 96 | |
| 97 | /* There are no parameters from BL2 if BL31 is a reset vector */ |
Antonio Nino Diaz | 012c8bf | 2018-09-24 17:16:52 +0100 | [diff] [blame] | 98 | assert(arg0 == 0U); |
| 99 | assert(arg1 == 0U); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 100 | |
| 101 | /* |
| 102 | * Do initial security configuration to allow DRAM/device access. On |
| 103 | * Base ZYNQMP only DRAM security is programmable (via TrustZone), but |
| 104 | * other platforms might have more programmable security devices |
| 105 | * present. |
| 106 | */ |
| 107 | |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 108 | /* Populate common information for BL32 and BL33 */ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 109 | SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); |
| 110 | SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 111 | SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 112 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| 113 | |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 114 | atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); |
| 115 | |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 116 | if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { |
Alistair Francis | b8d474f | 2017-11-30 16:21:21 -0800 | [diff] [blame] | 117 | bl31_set_default_config(); |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 118 | } else { |
| 119 | /* use parameters from FSBL */ |
Siva Durga Prasad Paladugu | 8f49972 | 2018-05-17 15:17:46 +0530 | [diff] [blame] | 120 | enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, |
Venkatesh Yadav Abbarapu | 1463dd5 | 2020-01-07 03:25:16 -0700 | [diff] [blame] | 121 | &bl33_image_ep_info, |
| 122 | atf_handoff_addr); |
Michal Simek | 7dd8d72 | 2023-02-20 13:01:27 +0100 | [diff] [blame] | 123 | if (ret != FSBL_HANDOFF_SUCCESS) { |
Siva Durga Prasad Paladugu | 8f49972 | 2018-05-17 15:17:46 +0530 | [diff] [blame] | 124 | panic(); |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 125 | } |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 126 | } |
Venkatesh Yadav Abbarapu | 3a33f93 | 2022-05-04 14:27:56 +0530 | [diff] [blame] | 127 | if (bl32_image_ep_info.pc != 0) { |
Akshay Belsare | de7a1cc | 2023-03-27 10:41:54 +0530 | [diff] [blame] | 128 | NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); |
Venkatesh Yadav Abbarapu | 621c1b2 | 2020-01-10 03:01:35 -0700 | [diff] [blame] | 129 | } |
Venkatesh Yadav Abbarapu | 3a33f93 | 2022-05-04 14:27:56 +0530 | [diff] [blame] | 130 | if (bl33_image_ep_info.pc != 0) { |
Akshay Belsare | de7a1cc | 2023-03-27 10:41:54 +0530 | [diff] [blame] | 131 | NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); |
Venkatesh Yadav Abbarapu | 621c1b2 | 2020-01-10 03:01:35 -0700 | [diff] [blame] | 132 | } |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 133 | |
| 134 | custom_early_setup(); |
| 135 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 136 | } |
| 137 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 138 | #if ZYNQMP_WDT_RESTART |
| 139 | static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; |
| 140 | |
| 141 | int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) |
| 142 | { |
| 143 | /* Validate 'handler' and 'id' parameters */ |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 144 | if (!handler || id >= MAX_INTR_EL3) { |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 145 | return -EINVAL; |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 146 | } |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 147 | |
| 148 | /* Check if a handler has already been registered */ |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 149 | if (type_el3_interrupt_table[id]) { |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 150 | return -EALREADY; |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 151 | } |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 152 | |
| 153 | type_el3_interrupt_table[id] = handler; |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, |
| 159 | void *handle, void *cookie) |
| 160 | { |
| 161 | uint32_t intr_id; |
| 162 | interrupt_type_handler_t handler; |
| 163 | |
| 164 | intr_id = plat_ic_get_pending_interrupt_id(); |
| 165 | handler = type_el3_interrupt_table[intr_id]; |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 166 | if (handler != NULL) { |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 167 | handler(intr_id, flags, handle, cookie); |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 168 | } |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 169 | |
| 170 | return 0; |
| 171 | } |
| 172 | #endif |
| 173 | |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 174 | #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 175 | static void prepare_dtb(void) |
| 176 | { |
| 177 | void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; |
| 178 | int ret; |
| 179 | |
| 180 | /* Return if no device tree is detected */ |
| 181 | if (fdt_check_header(dtb) != 0) { |
Michal Simek | a76c5fd | 2022-09-14 09:29:50 +0200 | [diff] [blame] | 182 | NOTICE("Can't read DT at %p\n", dtb); |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 183 | return; |
| 184 | } |
| 185 | |
| 186 | ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE); |
| 187 | if (ret < 0) { |
| 188 | ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); |
| 189 | return; |
| 190 | } |
| 191 | |
| 192 | if (dt_add_psci_node(dtb)) { |
| 193 | ERROR("Failed to add PSCI Device Tree node\n"); |
| 194 | return; |
| 195 | } |
| 196 | |
| 197 | if (dt_add_psci_cpu_enable_methods(dtb)) { |
| 198 | ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | /* Reserve memory used by Trusted Firmware. */ |
Michal Simek | 7c75489 | 2023-02-13 13:11:28 +0100 | [diff] [blame] | 203 | if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, |
| 204 | BL31_LIMIT - BL31_BASE + 1)) { |
| 205 | WARN("Failed to add reserved memory nodes for BL31 to DT.\n"); |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | ret = fdt_pack(dtb); |
| 209 | if (ret < 0) { |
| 210 | ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); |
| 211 | } |
| 212 | |
| 213 | clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); |
| 214 | INFO("Changed device tree to advertise PSCI and reserved memories.\n"); |
| 215 | } |
| 216 | #endif |
| 217 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 218 | void bl31_platform_setup(void) |
| 219 | { |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 220 | #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) |
Michal Simek | eb2c0c0 | 2023-02-13 14:35:21 +0100 | [diff] [blame] | 221 | prepare_dtb(); |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 222 | #endif |
| 223 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 224 | /* Initialize the gic cpu and distributor interfaces */ |
| 225 | plat_arm_gic_driver_init(); |
| 226 | plat_arm_gic_init(); |
| 227 | } |
| 228 | |
| 229 | void bl31_plat_runtime_setup(void) |
| 230 | { |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 231 | #if ZYNQMP_WDT_RESTART |
| 232 | uint64_t flags = 0; |
| 233 | uint64_t rc; |
| 234 | |
| 235 | set_interrupt_rm_flag(flags, NON_SECURE); |
| 236 | rc = register_interrupt_type_handler(INTR_TYPE_EL3, |
| 237 | rdo_el3_interrupt_handler, flags); |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 238 | if (rc) { |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 239 | panic(); |
Venkatesh Yadav Abbarapu | 5f115db | 2021-01-10 20:40:16 -0700 | [diff] [blame] | 240 | } |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 241 | #endif |
Akshay Belsare | e8af4da | 2023-04-06 11:09:20 +0530 | [diff] [blame] | 242 | |
| 243 | custom_runtime_setup(); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | /* |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 247 | * Perform the very early platform specific architectural setup here. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 248 | */ |
| 249 | void bl31_plat_arch_setup(void) |
| 250 | { |
| 251 | plat_arm_interconnect_init(); |
| 252 | plat_arm_interconnect_enter_coherency(); |
| 253 | |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 254 | const mmap_region_t bl_regions[] = { |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 255 | #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 256 | MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, |
| 257 | MT_MEMORY | MT_RW | MT_NS), |
| 258 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 259 | MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, |
| 260 | MT_MEMORY | MT_RW | MT_SECURE), |
| 261 | MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, |
| 262 | MT_CODE | MT_SECURE), |
| 263 | MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, |
| 264 | MT_RO_DATA | MT_SECURE), |
| 265 | MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, |
| 266 | BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
| 267 | MT_DEVICE | MT_RW | MT_SECURE), |
| 268 | {0} |
| 269 | }; |
| 270 | |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 271 | custom_mmap_add(); |
| 272 | |
Roberto Vargas | 344ff02 | 2018-10-19 16:44:18 +0100 | [diff] [blame] | 273 | setup_page_tables(bl_regions, plat_arm_get_mmap()); |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 274 | enable_mmu_el3(0); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 275 | } |