| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __FLOWCTRL_H__ |
| 32 | #define __FLOWCTRL_H__ |
| 33 | |
| 34 | #include <mmio.h> |
| 35 | #include <tegra_def.h> |
| 36 | |
| 37 | #define FLOWCTRL_HALT_CPU0_EVENTS 0x0 |
| 38 | #define FLOWCTRL_WAITEVENT (2 << 29) |
| 39 | #define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29) |
| 40 | #define FLOWCTRL_JTAG_RESUME (1 << 28) |
| 41 | #define FLOWCTRL_HALT_SCLK (1 << 27) |
| 42 | #define FLOWCTRL_HALT_LIC_IRQ (1 << 11) |
| 43 | #define FLOWCTRL_HALT_LIC_FIQ (1 << 10) |
| 44 | #define FLOWCTRL_HALT_GIC_IRQ (1 << 9) |
| 45 | #define FLOWCTRL_HALT_GIC_FIQ (1 << 8) |
| 46 | #define FLOWCTRL_HALT_BPMP_EVENTS 0x4 |
| 47 | #define FLOWCTRL_CPU0_CSR 0x8 |
| 48 | #define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16) |
| 49 | #define FLOWCTRL_CSR_INTR_FLAG (1 << 15) |
| 50 | #define FLOWCTRL_CSR_EVENT_FLAG (1 << 14) |
| 51 | #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3) |
| 52 | #define FLOWCTRL_CSR_ENABLE (1 << 0) |
| 53 | #define FLOWCTRL_HALT_CPU1_EVENTS 0x14 |
| 54 | #define FLOWCTRL_CPU1_CSR 0x18 |
| 55 | #define FLOWCTRL_CC4_CORE0_CTRL 0x6c |
| 56 | #define FLOWCTRL_WAIT_WFI_BITMAP 0x100 |
| 57 | #define FLOWCTRL_L2_FLUSH_CONTROL 0x94 |
| 58 | #define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98 |
| 59 | #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2) |
| 60 | |
| 61 | #define FLOWCTRL_ENABLE_EXT 12 |
| 62 | #define FLOWCTRL_ENABLE_EXT_MASK 3 |
| 63 | #define FLOWCTRL_PG_CPU_NONCPU 0x1 |
| 64 | #define FLOWCTRL_TURNOFF_CPURAIL 0x2 |
| 65 | |
| 66 | static inline uint32_t tegra_fc_read_32(uint32_t off) |
| 67 | { |
| 68 | return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); |
| 69 | } |
| 70 | |
| 71 | static inline void tegra_fc_write_32(uint32_t off, uint32_t val) |
| 72 | { |
| 73 | mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); |
| 74 | } |
| 75 | |
| 76 | void tegra_fc_cpu_idle(uint32_t mpidr); |
| 77 | void tegra_fc_cluster_idle(uint32_t midr); |
| 78 | void tegra_fc_cluster_powerdn(uint32_t midr); |
| 79 | void tegra_fc_soc_powerdn(uint32_t midr); |
| 80 | void tegra_fc_cpu_on(int cpu); |
| 81 | void tegra_fc_cpu_off(int cpu); |
| 82 | void tegra_fc_lock_active_cluster(void); |
| 83 | void tegra_fc_reset_bpmp(void); |
| 84 | |
| 85 | #endif /* __FLOWCTRL_H__ */ |