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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <utils_def.h>
11
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(24)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_REV_SHIFT U(0)
20#define MIDR_REV_BITS U(4)
21#define MIDR_PN_MASK U(0xfff)
22#define MIDR_PN_SHIFT U(4)
Soby Mathewc6820d12016-05-09 17:49:55 +010023
24/*******************************************************************************
25 * MPIDR macros
26 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010027#define MPIDR_MT_MASK (U(1) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010028#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_AFFINITY_BITS U(8)
31#define MPIDR_AFFLVL_MASK U(0xff)
32#define MPIDR_AFFLVL_SHIFT U(3)
33#define MPIDR_AFF0_SHIFT U(0)
34#define MPIDR_AFF1_SHIFT U(8)
35#define MPIDR_AFF2_SHIFT U(16)
36#define MPIDR_AFFINITY_MASK U(0x00ffffff)
37#define MPIDR_AFFLVL0 U(0)
38#define MPIDR_AFFLVL1 U(1)
39#define MPIDR_AFFLVL2 U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010040
41#define MPIDR_AFFLVL0_VAL(mpidr) \
42 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
43#define MPIDR_AFFLVL1_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
45#define MPIDR_AFFLVL2_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010047#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
Soby Mathewc6820d12016-05-09 17:49:55 +010048
49/*
50 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
51 * add one while using this macro to define array sizes.
52 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010053#define MPIDR_MAX_AFFLVL U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010054
55/* Data Cache set/way op type defines */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010056#define DC_OP_ISW U(0x0)
57#define DC_OP_CISW U(0x1)
58#define DC_OP_CSW U(0x2)
Soby Mathewc6820d12016-05-09 17:49:55 +010059
60/*******************************************************************************
61 * Generic timer memory mapped registers & offsets
62 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010063#define CNTCR_OFF U(0x000)
64#define CNTFID_OFF U(0x020)
Soby Mathewc6820d12016-05-09 17:49:55 +010065
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010066#define CNTCR_EN (U(1) << 0)
67#define CNTCR_HDBG (U(1) << 1)
Soby Mathewc6820d12016-05-09 17:49:55 +010068#define CNTCR_FCREQ(x) ((x) << 8)
69
70/*******************************************************************************
71 * System register bit definitions
72 ******************************************************************************/
73/* CLIDR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010074#define LOUIS_SHIFT U(21)
75#define LOC_SHIFT U(24)
76#define CLIDR_FIELD_WIDTH U(3)
Soby Mathewc6820d12016-05-09 17:49:55 +010077
78/* CSSELR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010079#define LEVEL_SHIFT U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +010080
Dimitris Papastamosdda48b02017-10-17 14:03:14 +010081/* ID_PFR0 definitions */
82#define ID_PFR0_AMU_SHIFT U(20)
83#define ID_PFR0_AMU_LENGTH U(4)
84#define ID_PFR0_AMU_MASK U(0xf)
85
Soby Mathewc6820d12016-05-09 17:49:55 +010086/* ID_PFR1 definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010087#define ID_PFR1_VIRTEXT_SHIFT U(12)
88#define ID_PFR1_VIRTEXT_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +010089#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
90 & ID_PFR1_VIRTEXT_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010091#define ID_PFR1_GIC_SHIFT U(28)
92#define ID_PFR1_GIC_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +010093
94/* SCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010095#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
96 (U(1) << 3))
Etienne Carriere70a004b2017-11-05 22:56:03 +010097#if ARM_ARCH_MAJOR == 7
98#define SCTLR_RES1 SCTLR_RES1_DEF
99#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100100#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100101#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100102#define SCTLR_M_BIT (U(1) << 0)
103#define SCTLR_A_BIT (U(1) << 1)
104#define SCTLR_C_BIT (U(1) << 2)
105#define SCTLR_CP15BEN_BIT (U(1) << 5)
106#define SCTLR_ITD_BIT (U(1) << 7)
107#define SCTLR_Z_BIT (U(1) << 11)
108#define SCTLR_I_BIT (U(1) << 12)
109#define SCTLR_V_BIT (U(1) << 13)
110#define SCTLR_RR_BIT (U(1) << 14)
111#define SCTLR_NTWI_BIT (U(1) << 16)
112#define SCTLR_NTWE_BIT (U(1) << 18)
113#define SCTLR_WXN_BIT (U(1) << 19)
114#define SCTLR_UWXN_BIT (U(1) << 20)
115#define SCTLR_EE_BIT (U(1) << 25)
116#define SCTLR_TRE_BIT (U(1) << 28)
117#define SCTLR_AFE_BIT (U(1) << 29)
118#define SCTLR_TE_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100119#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
120 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100121
dp-arm595d0d52017-02-08 11:51:50 +0000122/* SDCR definitions */
123#define SDCR_SPD(x) ((x) << 14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100124#define SDCR_SPD_LEGACY U(0x0)
125#define SDCR_SPD_DISABLE U(0x2)
126#define SDCR_SPD_ENABLE U(0x3)
127#define SDCR_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000128
David Cunadofee86532017-04-13 22:38:29 +0100129#if !ERROR_DEPRECATED
dp-arm595d0d52017-02-08 11:51:50 +0000130#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
David Cunadofee86532017-04-13 22:38:29 +0100131#endif
dp-arm595d0d52017-02-08 11:51:50 +0000132
Soby Mathewc6820d12016-05-09 17:49:55 +0100133/* HSCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100134#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
135 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
136 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
137
138#define HSCTLR_M_BIT (U(1) << 0)
139#define HSCTLR_A_BIT (U(1) << 1)
140#define HSCTLR_C_BIT (U(1) << 2)
141#define HSCTLR_CP15BEN_BIT (U(1) << 5)
142#define HSCTLR_ITD_BIT (U(1) << 7)
143#define HSCTLR_SED_BIT (U(1) << 8)
144#define HSCTLR_I_BIT (U(1) << 12)
145#define HSCTLR_WXN_BIT (U(1) << 19)
146#define HSCTLR_EE_BIT (U(1) << 25)
147#define HSCTLR_TE_BIT (U(1) << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100148
149/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100150#define CPACR_FPEN(x) ((x) << 20)
151#define CPACR_FP_TRAP_PL0 U(0x1)
152#define CPACR_FP_TRAP_ALL U(0x2)
153#define CPACR_FP_TRAP_NONE U(0x3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100154
155/* SCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100156#define SCR_TWE_BIT (U(1) << 13)
157#define SCR_TWI_BIT (U(1) << 12)
158#define SCR_SIF_BIT (U(1) << 9)
159#define SCR_HCE_BIT (U(1) << 8)
160#define SCR_SCD_BIT (U(1) << 7)
161#define SCR_NET_BIT (U(1) << 6)
162#define SCR_AW_BIT (U(1) << 5)
163#define SCR_FW_BIT (U(1) << 4)
164#define SCR_EA_BIT (U(1) << 3)
165#define SCR_FIQ_BIT (U(1) << 2)
166#define SCR_IRQ_BIT (U(1) << 1)
167#define SCR_NS_BIT (U(1) << 0)
168#define SCR_VALID_BIT_MASK U(0x33ff)
169#define SCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100170
171#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
172
173/* HCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100174#define HCR_AMO_BIT (U(1) << 5)
175#define HCR_IMO_BIT (U(1) << 4)
176#define HCR_FMO_BIT (U(1) << 3)
177#define HCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100178
179/* CNTHCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100180#define CNTHCTL_RESET_VAL U(0x0)
181#define PL1PCEN_BIT (U(1) << 1)
182#define PL1PCTEN_BIT (U(1) << 0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100183
184/* CNTKCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100185#define PL0PTEN_BIT (U(1) << 9)
186#define PL0VTEN_BIT (U(1) << 8)
187#define PL0PCTEN_BIT (U(1) << 0)
188#define PL0VCTEN_BIT (U(1) << 1)
189#define EVNTEN_BIT (U(1) << 2)
190#define EVNTDIR_BIT (U(1) << 3)
191#define EVNTI_SHIFT U(4)
192#define EVNTI_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100193
194/* HCPTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100195#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
196#define TCPAC_BIT (U(1) << 31)
197#define TAM_BIT (U(1) << 30)
198#define TTA_BIT (U(1) << 20)
Sandrine Bailleux6061c452018-07-13 10:04:12 +0200199#define TCP11_BIT (U(1) << 11)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100200#define TCP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100201#define HCPTR_RESET_VAL HCPTR_RES1
202
203/* VTTBR defintions */
204#define VTTBR_RESET_VAL ULL(0x0)
205#define VTTBR_VMID_MASK ULL(0xff)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100206#define VTTBR_VMID_SHIFT U(48)
207#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
208#define VTTBR_BADDR_SHIFT U(0)
David Cunadofee86532017-04-13 22:38:29 +0100209
210/* HDCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100211#define HDCR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100212
213/* HSTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100214#define HSTR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100215
216/* CNTHP_CTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100217#define CNTHP_CTL_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100218
219/* NASCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100220#define NSASEDIS_BIT (U(1) << 15)
221#define NSTRCDIS_BIT (U(1) << 20)
David Cunadofee86532017-04-13 22:38:29 +0100222/* NOTE: correct typo in the definitions */
223#if !ERROR_DEPRECATED
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100224#define NASCR_CP11_BIT (U(1) << 11)
225#define NASCR_CP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100226#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100227#define NSACR_CP11_BIT (U(1) << 11)
228#define NSACR_CP10_BIT (U(1) << 10)
229#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
David Cunadofee86532017-04-13 22:38:29 +0100230#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100231#define NSACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100232
233/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100234#define ASEDIS_BIT (U(1) << 31)
235#define TRCDIS_BIT (U(1) << 28)
236#define CPACR_CP11_SHIFT U(22)
237#define CPACR_CP10_SHIFT U(20)
238#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
239 (U(0x3) << CPACR_CP10_SHIFT))
240#define CPACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100241
242/* FPEXC definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100243#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
244#define FPEXC_EN_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100245#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100246
247/* SPSR/CPSR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100248#define SPSR_FIQ_BIT (U(1) << 0)
249#define SPSR_IRQ_BIT (U(1) << 1)
250#define SPSR_ABT_BIT (U(1) << 2)
251#define SPSR_AIF_SHIFT U(6)
252#define SPSR_AIF_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100253
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100254#define SPSR_E_SHIFT U(9)
255#define SPSR_E_MASK U(0x1)
256#define SPSR_E_LITTLE U(0)
257#define SPSR_E_BIG U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100258
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100259#define SPSR_T_SHIFT U(5)
260#define SPSR_T_MASK U(0x1)
261#define SPSR_T_ARM U(0)
262#define SPSR_T_THUMB U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100263
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100264#define SPSR_MODE_SHIFT U(0)
265#define SPSR_MODE_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100266
267#define DISABLE_ALL_EXCEPTIONS \
268 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
269
270/*
271 * TTBCR definitions
272 */
273/* The ARM Trusted Firmware uses the long descriptor format */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100274#define TTBCR_EAE_BIT (U(1) << 31)
Soby Mathewc6820d12016-05-09 17:49:55 +0100275
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100276#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
277#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
278#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
Soby Mathewc6820d12016-05-09 17:49:55 +0100279
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100280#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
281#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
282#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
283#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
Soby Mathewc6820d12016-05-09 17:49:55 +0100284
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100285#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
286#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
287#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
288#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +0100289
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100290#define TTBCR_EPD1_BIT (U(1) << 23)
291#define TTBCR_A1_BIT (U(1) << 22)
Soby Mathewc6820d12016-05-09 17:49:55 +0100292
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100293#define TTBCR_T1SZ_SHIFT U(16)
294#define TTBCR_T1SZ_MASK U(0x7)
295#define TTBCR_TxSZ_MIN U(0)
296#define TTBCR_TxSZ_MAX U(7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100297
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100298#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
299#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
300#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
Soby Mathewc6820d12016-05-09 17:49:55 +0100301
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100302#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
303#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
304#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
305#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
Soby Mathewc6820d12016-05-09 17:49:55 +0100306
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100307#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
308#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
309#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
310#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
Soby Mathewc6820d12016-05-09 17:49:55 +0100311
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100312#define TTBCR_EPD0_BIT (U(1) << 7)
313#define TTBCR_T0SZ_SHIFT U(0)
314#define TTBCR_T0SZ_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100315
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100316/*
317 * HTCR definitions
318 */
319#define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
320
321#define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
322#define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
323#define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
324
325#define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
326#define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
327#define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
328#define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
329
330#define HTCR_RGN0_INNER_NC (U(0x0) << 8)
331#define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
332#define HTCR_RGN0_INNER_WT (U(0x2) << 8)
333#define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
334
335#define HTCR_T0SZ_SHIFT U(0)
336#define HTCR_T0SZ_MASK U(0x7)
337
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100338#define MODE_RW_SHIFT U(0x4)
339#define MODE_RW_MASK U(0x1)
340#define MODE_RW_32 U(0x1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100341
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100342#define MODE32_SHIFT U(0)
343#define MODE32_MASK U(0x1f)
344#define MODE32_usr U(0x10)
345#define MODE32_fiq U(0x11)
346#define MODE32_irq U(0x12)
347#define MODE32_svc U(0x13)
348#define MODE32_mon U(0x16)
349#define MODE32_abt U(0x17)
350#define MODE32_hyp U(0x1a)
351#define MODE32_und U(0x1b)
352#define MODE32_sys U(0x1f)
Soby Mathewc6820d12016-05-09 17:49:55 +0100353
354#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
355
356#define SPSR_MODE32(mode, isa, endian, aif) \
357 (MODE_RW_32 << MODE_RW_SHIFT | \
358 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
359 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
360 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
361 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
362
363/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100364 * TTBR definitions
365 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100366#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100367
368/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100369 * CTR definitions
370 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100371#define CTR_CWG_SHIFT U(24)
372#define CTR_CWG_MASK U(0xf)
373#define CTR_ERG_SHIFT U(20)
374#define CTR_ERG_MASK U(0xf)
375#define CTR_DMINLINE_SHIFT U(16)
376#define CTR_DMINLINE_WIDTH U(4)
377#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
378#define CTR_L1IP_SHIFT U(14)
379#define CTR_L1IP_MASK U(0x3)
380#define CTR_IMINLINE_SHIFT U(0)
381#define CTR_IMINLINE_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100382
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100383#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Soby Mathewc6820d12016-05-09 17:49:55 +0100384
David Cunado5f55e282016-10-31 17:37:34 +0000385/* PMCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100386#define PMCR_N_SHIFT U(11)
387#define PMCR_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000388#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100389#define PMCR_LC_BIT (U(1) << 6)
390#define PMCR_DP_BIT (U(1) << 5)
David Cunado5f55e282016-10-31 17:37:34 +0000391
Soby Mathewc6820d12016-05-09 17:49:55 +0100392/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000393 * Definitions of register offsets, fields and macros for CPU system
394 * instructions.
395 ******************************************************************************/
396
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100397#define TLBI_ADDR_SHIFT U(0)
398#define TLBI_ADDR_MASK U(0xFFFFF000)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000399#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
400
401/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100402 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
403 * system level implementation of the Generic Timer.
404 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100405#define CNTCTLBASE_CNTFRQ U(0x0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100406#define CNTNSAR U(0x4)
Soby Mathewc6820d12016-05-09 17:49:55 +0100407#define CNTNSAR_NS_SHIFT(x) (x)
408
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100409#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
410#define CNTACR_RPCT_SHIFT U(0x0)
411#define CNTACR_RVCT_SHIFT U(0x1)
412#define CNTACR_RFRQ_SHIFT U(0x2)
413#define CNTACR_RVOFF_SHIFT U(0x3)
414#define CNTACR_RWVT_SHIFT U(0x4)
415#define CNTACR_RWPT_SHIFT U(0x5)
Soby Mathewc6820d12016-05-09 17:49:55 +0100416
Soby Mathew2d9f7952018-06-11 16:21:30 +0100417/*******************************************************************************
418 * Definitions of register offsets in the CNTBaseN Frame of the
419 * system level implementation of the Generic Timer.
420 ******************************************************************************/
421#define CNTBASE_CNTFRQ U(0x10)
422
Soby Mathewc6820d12016-05-09 17:49:55 +0100423/* MAIR macros */
424#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100425#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << 3))
Soby Mathewc6820d12016-05-09 17:49:55 +0100426
427/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
428#define SCR p15, 0, c1, c1, 0
429#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100430#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000431#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100432#define MPIDR p15, 0, c0, c0, 5
433#define MIDR p15, 0, c0, c0, 0
434#define VBAR p15, 0, c12, c0, 0
435#define MVBAR p15, 0, c12, c0, 1
436#define NSACR p15, 0, c1, c1, 2
437#define CPACR p15, 0, c1, c0, 2
438#define DCCIMVAC p15, 0, c7, c14, 1
439#define DCCMVAC p15, 0, c7, c10, 1
440#define DCIMVAC p15, 0, c7, c6, 1
441#define DCCISW p15, 0, c7, c14, 2
442#define DCCSW p15, 0, c7, c10, 2
443#define DCISW p15, 0, c7, c6, 2
444#define CTR p15, 0, c0, c0, 1
445#define CNTFRQ p15, 0, c14, c0, 0
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100446#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100447#define ID_PFR1 p15, 0, c0, c1, 1
448#define MAIR0 p15, 0, c10, c2, 0
449#define MAIR1 p15, 0, c10, c2, 1
450#define TTBCR p15, 0, c2, c0, 2
451#define TTBR0 p15, 0, c2, c0, 0
452#define TTBR1 p15, 0, c2, c0, 1
453#define TLBIALL p15, 0, c8, c7, 0
454#define TLBIALLIS p15, 0, c8, c3, 0
455#define TLBIMVA p15, 0, c8, c7, 1
456#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000457#define TLBIMVAAIS p15, 0, c8, c3, 3
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100458#define TLBIMVAHIS p15, 4, c8, c3, 1
Antonio Nino Diazac998032017-02-27 17:23:54 +0000459#define BPIALLIS p15, 0, c7, c1, 6
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000460#define BPIALL p15, 0, c7, c5, 6
461#define ICIALLU p15, 0, c7, c5, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100462#define HSCTLR p15, 4, c1, c0, 0
463#define HCR p15, 4, c1, c1, 0
464#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100465#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100466#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000467#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100468#define VPIDR p15, 4, c0, c0, 0
469#define VMPIDR p15, 4, c0, c0, 5
470#define ISR p15, 0, c12, c1, 0
471#define CLIDR p15, 1, c0, c0, 1
472#define CSSELR p15, 2, c0, c0, 0
473#define CCSIDR p15, 1, c0, c0, 0
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100474#define HTCR p15, 4, c2, c0, 2
475#define HMAIR0 p15, 4, c10, c2, 0
Douglas Raillard77414632018-08-21 12:54:45 +0100476#define ATS1CPR p15, 0, c7, c8, 0
477#define ATS1HR p15, 4, c7, c8, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000478#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100479
David Cunado5f55e282016-10-31 17:37:34 +0000480/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
481#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000482#define PMCR p15, 0, c9, c12, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000483#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000484
Etienne Carriere70a004b2017-11-05 22:56:03 +0100485/* AArch32 coproc registers for 32bit MMU descriptor support */
486#define PRRR p15, 0, c10, c2, 0
487#define NMRR p15, 0, c10, c2, 1
488#define DACR p15, 0, c3, c0, 0
489
Soby Mathewc6820d12016-05-09 17:49:55 +0100490/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
491#define ICC_IAR1 p15, 0, c12, c12, 0
492#define ICC_IAR0 p15, 0, c12, c8, 0
493#define ICC_EOIR1 p15, 0, c12, c12, 1
494#define ICC_EOIR0 p15, 0, c12, c8, 1
495#define ICC_HPPIR1 p15, 0, c12, c12, 2
496#define ICC_HPPIR0 p15, 0, c12, c8, 2
497#define ICC_BPR1 p15, 0, c12, c12, 3
498#define ICC_BPR0 p15, 0, c12, c8, 3
499#define ICC_DIR p15, 0, c12, c11, 1
500#define ICC_PMR p15, 0, c4, c6, 0
501#define ICC_RPR p15, 0, c12, c11, 3
502#define ICC_CTLR p15, 0, c12, c12, 4
503#define ICC_MCTLR p15, 6, c12, c12, 4
504#define ICC_SRE p15, 0, c12, c12, 5
505#define ICC_HSRE p15, 4, c12, c9, 5
506#define ICC_MSRE p15, 6, c12, c12, 5
507#define ICC_IGRPEN0 p15, 0, c12, c12, 6
508#define ICC_IGRPEN1 p15, 0, c12, c12, 7
509#define ICC_MGRPEN1 p15, 6, c12, c12, 7
510
511/* 64 bit system register defines The format is: coproc, opt1, CRm */
512#define TTBR0_64 p15, 0, c2
513#define TTBR1_64 p15, 1, c2
514#define CNTVOFF_64 p15, 4, c14
515#define VTTBR_64 p15, 6, c2
516#define CNTPCT_64 p15, 0, c14
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100517#define HTTBR_64 p15, 4, c2
Douglas Raillard77414632018-08-21 12:54:45 +0100518#define PAR_64 p15, 0, c7
Soby Mathewc6820d12016-05-09 17:49:55 +0100519
520/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
521#define ICC_SGI1R_EL1_64 p15, 0, c12
522#define ICC_ASGI1R_EL1_64 p15, 1, c12
523#define ICC_SGI0R_EL1_64 p15, 2, c12
524
Isla Mitchell02c63072017-07-21 14:44:36 +0100525/*******************************************************************************
526 * Definitions of MAIR encodings for device and normal memory
527 ******************************************************************************/
528/*
529 * MAIR encodings for device memory attributes.
530 */
531#define MAIR_DEV_nGnRnE U(0x0)
532#define MAIR_DEV_nGnRE U(0x4)
533#define MAIR_DEV_nGRE U(0x8)
534#define MAIR_DEV_GRE U(0xc)
535
536/*
537 * MAIR encodings for normal memory attributes.
538 *
539 * Cache Policy
540 * WT: Write Through
541 * WB: Write Back
542 * NC: Non-Cacheable
543 *
544 * Transient Hint
545 * NTR: Non-Transient
546 * TR: Transient
547 *
548 * Allocation Policy
549 * RA: Read Allocate
550 * WA: Write Allocate
551 * RWA: Read and Write Allocate
552 * NA: No Allocation
553 */
554#define MAIR_NORM_WT_TR_WA U(0x1)
555#define MAIR_NORM_WT_TR_RA U(0x2)
556#define MAIR_NORM_WT_TR_RWA U(0x3)
557#define MAIR_NORM_NC U(0x4)
558#define MAIR_NORM_WB_TR_WA U(0x5)
559#define MAIR_NORM_WB_TR_RA U(0x6)
560#define MAIR_NORM_WB_TR_RWA U(0x7)
561#define MAIR_NORM_WT_NTR_NA U(0x8)
562#define MAIR_NORM_WT_NTR_WA U(0x9)
563#define MAIR_NORM_WT_NTR_RA U(0xa)
564#define MAIR_NORM_WT_NTR_RWA U(0xb)
565#define MAIR_NORM_WB_NTR_NA U(0xc)
566#define MAIR_NORM_WB_NTR_WA U(0xd)
567#define MAIR_NORM_WB_NTR_RA U(0xe)
568#define MAIR_NORM_WB_NTR_RWA U(0xf)
569
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100570#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100571
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100572#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
573 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100574
Douglas Raillard77414632018-08-21 12:54:45 +0100575/* PAR fields */
576#define PAR_F_SHIFT U(0)
577#define PAR_F_MASK ULL(0x1)
578#define PAR_ADDR_SHIFT U(12)
Yann Gautier812c3252018-09-20 15:48:52 +0200579#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
Douglas Raillard77414632018-08-21 12:54:45 +0100580
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100581/*******************************************************************************
582 * Definitions for system register interface to AMU for ARMv8.4 onwards
583 ******************************************************************************/
584#define AMCR p15, 0, c13, c2, 0
585#define AMCFGR p15, 0, c13, c2, 1
586#define AMCGCR p15, 0, c13, c2, 2
587#define AMUSERENR p15, 0, c13, c2, 3
588#define AMCNTENCLR0 p15, 0, c13, c2, 4
589#define AMCNTENSET0 p15, 0, c13, c2, 5
590#define AMCNTENCLR1 p15, 0, c13, c3, 0
Joel Hutton0dcdd8d2017-12-21 15:21:20 +0000591#define AMCNTENSET1 p15, 0, c13, c3, 1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100592
593/* Activity Monitor Group 0 Event Counter Registers */
594#define AMEVCNTR00 p15, 0, c0
595#define AMEVCNTR01 p15, 1, c0
596#define AMEVCNTR02 p15, 2, c0
597#define AMEVCNTR03 p15, 3, c0
598
599/* Activity Monitor Group 0 Event Type Registers */
600#define AMEVTYPER00 p15, 0, c13, c6, 0
601#define AMEVTYPER01 p15, 0, c13, c6, 1
602#define AMEVTYPER02 p15, 0, c13, c6, 2
603#define AMEVTYPER03 p15, 0, c13, c6, 3
604
Joel Hutton2691bc62017-12-12 15:47:55 +0000605/* Activity Monitor Group 1 Event Counter Registers */
606#define AMEVCNTR10 p15, 0, c4
607#define AMEVCNTR11 p15, 1, c4
608#define AMEVCNTR12 p15, 2, c4
609#define AMEVCNTR13 p15, 3, c4
610#define AMEVCNTR14 p15, 4, c4
611#define AMEVCNTR15 p15, 5, c4
612#define AMEVCNTR16 p15, 6, c4
613#define AMEVCNTR17 p15, 7, c4
614#define AMEVCNTR18 p15, 0, c5
615#define AMEVCNTR19 p15, 1, c5
616#define AMEVCNTR1A p15, 2, c5
617#define AMEVCNTR1B p15, 3, c5
618#define AMEVCNTR1C p15, 4, c5
619#define AMEVCNTR1D p15, 5, c5
620#define AMEVCNTR1E p15, 6, c5
621#define AMEVCNTR1F p15, 7, c5
622
623/* Activity Monitor Group 1 Event Type Registers */
624#define AMEVTYPER10 p15, 0, c13, c14, 0
625#define AMEVTYPER11 p15, 0, c13, c14, 1
626#define AMEVTYPER12 p15, 0, c13, c14, 2
627#define AMEVTYPER13 p15, 0, c13, c14, 3
628#define AMEVTYPER14 p15, 0, c13, c14, 4
629#define AMEVTYPER15 p15, 0, c13, c14, 5
630#define AMEVTYPER16 p15, 0, c13, c14, 6
631#define AMEVTYPER17 p15, 0, c13, c14, 7
632#define AMEVTYPER18 p15, 0, c13, c15, 0
633#define AMEVTYPER19 p15, 0, c13, c15, 1
634#define AMEVTYPER1A p15, 0, c13, c15, 2
635#define AMEVTYPER1B p15, 0, c13, c15, 3
636#define AMEVTYPER1C p15, 0, c13, c15, 4
637#define AMEVTYPER1D p15, 0, c13, c15, 5
638#define AMEVTYPER1E p15, 0, c13, c15, 6
639#define AMEVTYPER1F p15, 0, c13, c15, 7
640
Soby Mathewc6820d12016-05-09 17:49:55 +0100641#endif /* __ARCH_H__ */