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git01.mediatek.com / filogic / atf / 3b31b9350bd2c09e421d7aa7f0fe0a217d26ba70 / . / plat / mediatek / include / mt8188 / platform_def.h
blob: 3e82cefddcf26e94177b6281b794fe7979784e26 [file] [log] [blame]
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]1/*
2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
developer3b31b932022-09-05 16:07:00 +0800[diff] [blame^]10#include <arch_def.h>
11
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]12#define PLAT_PRIMARY_CPU (0x0)
13
14#define MT_GIC_BASE (0x0C000000)
15#define MCUCFG_BASE (0x0C530000)
16#define IO_PHYS (0x10000000)
17
18/* Aggregate of all devices for MMU mapping */
19#define MTK_DEV_RNG0_BASE (MT_GIC_BASE)
20#define MTK_DEV_RNG0_SIZE (0x600000)
21#define MTK_DEV_RNG1_BASE (IO_PHYS)
22#define MTK_DEV_RNG1_SIZE (0x10000000)
23
24/*******************************************************************************
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]25 * GPIO related constants
26 ******************************************************************************/
27#define GPIO_BASE (IO_PHYS + 0x00005000)
Fengquan Chen67f11f02022-08-17 10:42:15 +0800[diff] [blame]28#define RGU_BASE (IO_PHYS + 0x00007000)
29#define DRM_BASE (IO_PHYS + 0x0000D000)
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]30#define IOCFG_RM_BASE (IO_PHYS + 0x01C00000)
31#define IOCFG_LT_BASE (IO_PHYS + 0x01E10000)
32#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
33#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
34
35/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]36 * UART related constants
37 ******************************************************************************/
38#define UART0_BASE (IO_PHYS + 0x01002000)
39#define UART_BAUDRATE (115200)
40
41/*******************************************************************************
Hui Liu39ea6142022-07-28 20:28:32 +0800[diff] [blame]42 * PMIC related constants
43 ******************************************************************************/
44#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000)
45
46/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]47 * Infra IOMMU related constants
48 ******************************************************************************/
49#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
50#define PERICFG_AO_REG_SIZE (0x1000)
51
52/*******************************************************************************
developer66002552022-07-08 13:58:33 +0800[diff] [blame]53 * GIC-600 & interrupt handling related constants
54 ******************************************************************************/
55/* Base MTK_platform compatible GIC memory map */
56#define BASE_GICD_BASE (MT_GIC_BASE)
57#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
58
59/*******************************************************************************
developerbdeb0ba2022-07-08 14:48:56 +0800[diff] [blame]60 * CIRQ related constants
61 ******************************************************************************/
62#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
63#define MD_WDT_IRQ_BIT_ID (141)
64#define CIRQ_IRQ_NUM (730)
65#define CIRQ_REG_NUM (23)
66#define CIRQ_SPI_START (96)
67
68/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]69 * MM IOMMU & SMI related constants
70 ******************************************************************************/
71#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
72#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
73#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
74#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
75#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
76#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
77#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
78#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
79#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
80#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
81#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
82#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
83#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
84#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
85#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
86#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
87#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
88#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
89#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
90#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
91#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
92#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
93#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
94#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
95#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
96#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
97#define SMI_LARB_REG_RNG_SIZE (0x1000)
98
99/*******************************************************************************
developer7fa15de2022-07-11 19:03:35 +0800[diff] [blame]100 * DP related constants
101 ******************************************************************************/
102#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
103#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
104#define EDP_SEC_SIZE (0x1000)
105#define DP_SEC_SIZE (0x1000)
106
107/*******************************************************************************
developer880fb172022-09-05 19:08:59 +0800[diff] [blame]108 * EMI MPU related constants
109 *******************************************************************************/
110#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
111#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000)
112
113/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]114 * System counter frequency related constants
115 ******************************************************************************/
116#define SYS_COUNTER_FREQ_IN_HZ (13000000)
117#define SYS_COUNTER_FREQ_IN_MHZ (13)
118
119/*******************************************************************************
120 * Platform binary types for linking
121 ******************************************************************************/
122#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
123#define PLATFORM_LINKER_ARCH aarch64
124
125/*******************************************************************************
126 * Generic platform constants
127 ******************************************************************************/
128#define PLATFORM_STACK_SIZE (0x800)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]129#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]130#define SOC_CHIP_ID U(0x8188)
131
132/*******************************************************************************
133 * Platform memory map related constants
134 ******************************************************************************/
135#define TZRAM_BASE (0x54600000)
136#define TZRAM_SIZE (0x00030000)
137
138/*******************************************************************************
139 * BL31 specific defines.
140 ******************************************************************************/
141/*
142 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
143 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
144 * little space for growth.
145 */
146#define BL31_BASE (TZRAM_BASE + 0x1000)
147#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
148
149/*******************************************************************************
150 * Platform specific page table and MMU setup constants
151 ******************************************************************************/
152#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
153#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
154#define MAX_XLAT_TABLES (16)
155#define MAX_MMAP_REGIONS (16)
156
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]157#endif /* PLATFORM_DEF_H */