developer | 6d207b4 | 2022-07-07 19:30:22 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #define PLAT_PRIMARY_CPU (0x0) |
| 11 | |
| 12 | #define MT_GIC_BASE (0x0C000000) |
| 13 | #define MCUCFG_BASE (0x0C530000) |
| 14 | #define IO_PHYS (0x10000000) |
| 15 | |
| 16 | /* Aggregate of all devices for MMU mapping */ |
| 17 | #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) |
| 18 | #define MTK_DEV_RNG0_SIZE (0x600000) |
| 19 | #define MTK_DEV_RNG1_BASE (IO_PHYS) |
| 20 | #define MTK_DEV_RNG1_SIZE (0x10000000) |
| 21 | |
| 22 | /******************************************************************************* |
Jianguo Zhang | be99c73 | 2022-07-29 13:55:03 +0800 | [diff] [blame] | 23 | * GPIO related constants |
| 24 | ******************************************************************************/ |
| 25 | #define GPIO_BASE (IO_PHYS + 0x00005000) |
Fengquan Chen | 67f11f0 | 2022-08-17 10:42:15 +0800 | [diff] [blame^] | 26 | #define RGU_BASE (IO_PHYS + 0x00007000) |
| 27 | #define DRM_BASE (IO_PHYS + 0x0000D000) |
Jianguo Zhang | be99c73 | 2022-07-29 13:55:03 +0800 | [diff] [blame] | 28 | #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) |
| 29 | #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) |
| 30 | #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) |
| 31 | #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) |
| 32 | |
| 33 | /******************************************************************************* |
developer | 6d207b4 | 2022-07-07 19:30:22 +0800 | [diff] [blame] | 34 | * UART related constants |
| 35 | ******************************************************************************/ |
| 36 | #define UART0_BASE (IO_PHYS + 0x01002000) |
| 37 | #define UART_BAUDRATE (115200) |
| 38 | |
| 39 | /******************************************************************************* |
Hui Liu | 39ea614 | 2022-07-28 20:28:32 +0800 | [diff] [blame] | 40 | * PMIC related constants |
| 41 | ******************************************************************************/ |
| 42 | #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) |
| 43 | |
| 44 | /******************************************************************************* |
Chengci Xu | db1e75b | 2022-07-20 16:20:15 +0800 | [diff] [blame] | 45 | * Infra IOMMU related constants |
| 46 | ******************************************************************************/ |
| 47 | #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) |
| 48 | #define PERICFG_AO_REG_SIZE (0x1000) |
| 49 | |
| 50 | /******************************************************************************* |
developer | 6600255 | 2022-07-08 13:58:33 +0800 | [diff] [blame] | 51 | * GIC-600 & interrupt handling related constants |
| 52 | ******************************************************************************/ |
| 53 | /* Base MTK_platform compatible GIC memory map */ |
| 54 | #define BASE_GICD_BASE (MT_GIC_BASE) |
| 55 | #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) |
| 56 | |
| 57 | /******************************************************************************* |
developer | bdeb0ba | 2022-07-08 14:48:56 +0800 | [diff] [blame] | 58 | * CIRQ related constants |
| 59 | ******************************************************************************/ |
| 60 | #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) |
| 61 | #define MD_WDT_IRQ_BIT_ID (141) |
| 62 | #define CIRQ_IRQ_NUM (730) |
| 63 | #define CIRQ_REG_NUM (23) |
| 64 | #define CIRQ_SPI_START (96) |
| 65 | |
| 66 | /******************************************************************************* |
Chengci Xu | db1e75b | 2022-07-20 16:20:15 +0800 | [diff] [blame] | 67 | * MM IOMMU & SMI related constants |
| 68 | ******************************************************************************/ |
| 69 | #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) |
| 70 | #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) |
| 71 | #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) |
| 72 | #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) |
| 73 | #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) |
| 74 | #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) |
| 75 | #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) |
| 76 | #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) |
| 77 | #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) |
| 78 | #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) |
| 79 | #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) |
| 80 | #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) |
| 81 | #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) |
| 82 | #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) |
| 83 | #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) |
| 84 | #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) |
| 85 | #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) |
| 86 | #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) |
| 87 | #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) |
| 88 | #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) |
| 89 | #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) |
| 90 | #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) |
| 91 | #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) |
| 92 | #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) |
| 93 | #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) |
| 94 | #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) |
| 95 | #define SMI_LARB_REG_RNG_SIZE (0x1000) |
| 96 | |
| 97 | /******************************************************************************* |
developer | 7fa15de | 2022-07-11 19:03:35 +0800 | [diff] [blame] | 98 | * DP related constants |
| 99 | ******************************************************************************/ |
| 100 | #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) |
| 101 | #define DP_SEC_BASE (IO_PHYS + 0x0C604000) |
| 102 | #define EDP_SEC_SIZE (0x1000) |
| 103 | #define DP_SEC_SIZE (0x1000) |
| 104 | |
| 105 | /******************************************************************************* |
developer | 880fb17 | 2022-09-05 19:08:59 +0800 | [diff] [blame] | 106 | * EMI MPU related constants |
| 107 | *******************************************************************************/ |
| 108 | #define EMI_MPU_BASE (IO_PHYS + 0x00226000) |
| 109 | #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) |
| 110 | |
| 111 | /******************************************************************************* |
developer | 6d207b4 | 2022-07-07 19:30:22 +0800 | [diff] [blame] | 112 | * System counter frequency related constants |
| 113 | ******************************************************************************/ |
| 114 | #define SYS_COUNTER_FREQ_IN_HZ (13000000) |
| 115 | #define SYS_COUNTER_FREQ_IN_MHZ (13) |
| 116 | |
| 117 | /******************************************************************************* |
| 118 | * Platform binary types for linking |
| 119 | ******************************************************************************/ |
| 120 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 121 | #define PLATFORM_LINKER_ARCH aarch64 |
| 122 | |
| 123 | /******************************************************************************* |
| 124 | * Generic platform constants |
| 125 | ******************************************************************************/ |
| 126 | #define PLATFORM_STACK_SIZE (0x800) |
| 127 | |
| 128 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 129 | |
| 130 | #define PLAT_MAX_PWR_LVL U(3) |
| 131 | #define PLAT_MAX_RET_STATE U(1) |
| 132 | #define PLAT_MAX_OFF_STATE U(9) |
| 133 | |
| 134 | #define PLATFORM_SYSTEM_COUNT U(1) |
| 135 | #define PLATFORM_MCUSYS_COUNT U(1) |
| 136 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 137 | #define PLATFORM_CLUSTER0_CORE_COUNT U(8) |
| 138 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
| 139 | |
| 140 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) |
| 141 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) |
| 142 | |
| 143 | #define SOC_CHIP_ID U(0x8188) |
| 144 | |
| 145 | /******************************************************************************* |
| 146 | * Platform memory map related constants |
| 147 | ******************************************************************************/ |
| 148 | #define TZRAM_BASE (0x54600000) |
| 149 | #define TZRAM_SIZE (0x00030000) |
| 150 | |
| 151 | /******************************************************************************* |
| 152 | * BL31 specific defines. |
| 153 | ******************************************************************************/ |
| 154 | /* |
| 155 | * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if |
| 156 | * present). BL31_BASE is calculated using the current BL3-1 debug size plus a |
| 157 | * little space for growth. |
| 158 | */ |
| 159 | #define BL31_BASE (TZRAM_BASE + 0x1000) |
| 160 | #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 161 | |
| 162 | /******************************************************************************* |
| 163 | * Platform specific page table and MMU setup constants |
| 164 | ******************************************************************************/ |
| 165 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 166 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 167 | #define MAX_XLAT_TABLES (16) |
| 168 | #define MAX_MMAP_REGIONS (16) |
| 169 | |
| 170 | /******************************************************************************* |
| 171 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 172 | * aligned on the biggest cache line size in the platform. This is known only |
| 173 | * to the platform as it might have a combination of integrated and external |
| 174 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 175 | * line at any cache level. They could belong to different cpus/clusters & |
| 176 | * get written while being protected by different locks causing corruption of |
| 177 | * a valid mailbox address. |
| 178 | ******************************************************************************/ |
| 179 | #define CACHE_WRITEBACK_SHIFT (6) |
| 180 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 181 | |
| 182 | #endif /* PLATFORM_DEF_H */ |