blob: f567f02ef576b8faed3fca972f7a333d0a67719a [file] [log] [blame]
developera84a44a2020-08-19 17:20:15 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
developerceb197f2021-04-20 12:53:15 +08009#include <mtk_apusys.h>
developerafa342e2020-12-14 17:41:08 +080010#include <mtk_sip_svc.h>
11#include <mt_spm_vcorefs.h>
12#include "plat_sip_calls.h"
developera84a44a2020-08-19 17:20:15 +080013
14uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
15 u_register_t x1,
16 u_register_t x2,
17 u_register_t x3,
18 u_register_t x4,
19 void *cookie,
20 void *handle,
21 u_register_t flags)
22{
developerafa342e2020-12-14 17:41:08 +080023 uint64_t ret;
developerceb197f2021-04-20 12:53:15 +080024 uint32_t rnd_val0 = 0U;
developera84a44a2020-08-19 17:20:15 +080025
26 switch (smc_fid) {
developerafa342e2020-12-14 17:41:08 +080027 case MTK_SIP_VCORE_CONTROL_ARCH32:
28 case MTK_SIP_VCORE_CONTROL_ARCH64:
29 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
30 SMC_RET2(handle, ret, x4);
31 break;
developerceb197f2021-04-20 12:53:15 +080032 case MTK_SIP_APUSYS_CONTROL_AARCH32:
33 case MTK_SIP_APUSYS_CONTROL_AARCH64:
34 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
35 SMC_RET2(handle, ret, rnd_val0);
36 break;
developera84a44a2020-08-19 17:20:15 +080037 default:
38 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
39 break;
40 }
41
42 SMC_RET1(handle, SMC_UNK);
43}