| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. \ |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include "mtk_ptp3_common.h" |
| 8 | |
| 9 | /************************************************ |
| 10 | * Central control: turn on sysPi protection |
| 11 | ************************************************/ |
| 12 | static unsigned int ptp3_cfg1[NR_PTP3_CFG1_CPU][NR_PTP3_CFG] = { |
| 13 | {0x0C530610, 0x110842}, |
| 14 | {0x0C530E10, 0x110842}, |
| 15 | {0x0C531610, 0x110842}, |
| 16 | {0x0C531E10, 0x110842}, |
| 17 | {0x0C532610, 0x110842}, |
| 18 | {0x0C532E10, 0x110842}, |
| 19 | {0x0C533610, 0x110842}, |
| 20 | {0x0C533E10, 0x110842} |
| 21 | }; |
| 22 | static unsigned int ptp3_cfg2[NR_PTP3_CFG2_CPU][NR_PTP3_CFG] = { |
| 23 | {0x0C53B830, 0x68000}, |
| 24 | {0x0C53BA30, 0x68000}, |
| 25 | {0x0C53BC30, 0x68000}, |
| 26 | {0x0C53BE30, 0x68000} |
| 27 | }; |
| 28 | static unsigned int ptp3_cfg3[NR_PTP3_CFG3_CPU][NR_PTP3_CFG] = { |
| 29 | {0x0C532480, 0x7C607C6}, |
| 30 | {0x0C532C80, 0x7C607C6}, |
| 31 | {0x0C533480, 0x7C607C6}, |
| 32 | {0x0C533C80, 0x7C607C6} |
| 33 | }; |
| 34 | |
| 35 | /************************************************ |
| 36 | * API |
| 37 | ************************************************/ |
| 38 | void ptp3_init(unsigned int core) |
| 39 | { |
| 40 | unsigned int _core; |
| 41 | |
| developer | 35dfb09 | 2020-12-10 19:56:50 +0800 | [diff] [blame] | 42 | /* Apply ptp3_cfg1 for core 0 to 7 */ |
| 43 | if (core < NR_PTP3_CFG1_CPU) { |
| 44 | /* update ptp3_cfg1 */ |
| 45 | ptp3_write( |
| 46 | ptp3_cfg1[core][PTP3_CFG_ADDR], |
| 47 | ptp3_cfg1[core][PTP3_CFG_VALUE]); |
| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 48 | } |
| 49 | |
| developer | 35dfb09 | 2020-12-10 19:56:50 +0800 | [diff] [blame] | 50 | /* Apply ptp3_cfg2 for core 4 to 7 */ |
| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 51 | if (core >= PTP3_CFG2_CPU_START_ID) { |
| 52 | _core = core - PTP3_CFG2_CPU_START_ID; |
| 53 | |
| 54 | if (_core < NR_PTP3_CFG2_CPU) { |
| 55 | /* update ptp3_cfg2 */ |
| 56 | ptp3_write( |
| 57 | ptp3_cfg2[_core][PTP3_CFG_ADDR], |
| 58 | ptp3_cfg2[_core][PTP3_CFG_VALUE]); |
| 59 | } |
| 60 | } |
| 61 | |
| developer | 35dfb09 | 2020-12-10 19:56:50 +0800 | [diff] [blame] | 62 | /* Apply ptp3_cfg3 for core 4 to 7 */ |
| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 63 | if (core >= PTP3_CFG3_CPU_START_ID) { |
| 64 | _core = core - PTP3_CFG3_CPU_START_ID; |
| 65 | |
| 66 | if (_core < NR_PTP3_CFG3_CPU) { |
| 67 | /* update ptp3_cfg3 */ |
| 68 | ptp3_write( |
| 69 | ptp3_cfg3[_core][PTP3_CFG_ADDR], |
| 70 | ptp3_cfg3[_core][PTP3_CFG_VALUE]); |
| 71 | } |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | void ptp3_deinit(unsigned int core) |
| 76 | { |
| developer | 35dfb09 | 2020-12-10 19:56:50 +0800 | [diff] [blame] | 77 | if (core < NR_PTP3_CFG1_CPU) { |
| 78 | /* update ptp3_cfg1 */ |
| 79 | ptp3_write( |
| 80 | ptp3_cfg1[core][PTP3_CFG_ADDR], |
| 81 | ptp3_cfg1[core][PTP3_CFG_VALUE] & |
| 82 | ~PTP3_CFG1_MASK); |
| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 83 | } |
| 84 | } |