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git01.mediatek.com / filogic / atf / c6a11f687ddeed5c8fb91406db7f2a1ef52fc250 / . / plat / nvidia / tegra / include / t132 / tegra_def.h
blob: fcb074a78cde9f649edaad0d441070334f94d791 [file] [log] [blame]
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]5 */
6
7#ifndef __TEGRA_DEF_H__
8#define __TEGRA_DEF_H__
9
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]10/*******************************************************************************
11 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
12 * call as the `state-id` field in the 'power state' parameter.
13 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]14#define PSTATE_ID_SOC_POWERDN 0xD
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]15
16/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]17 * Platform power states (used by PSCI framework)
18 *
19 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
20 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
21 ******************************************************************************/
22#define PLAT_MAX_RET_STATE 1
23#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
24
25/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]26 * GIC memory map
27 ******************************************************************************/
28#define TEGRA_GICD_BASE 0x50041000
29#define TEGRA_GICC_BASE 0x50042000
30
31/*******************************************************************************
32 * Tegra micro-seconds timer constants
33 ******************************************************************************/
34#define TEGRA_TMRUS_BASE 0x60005010
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]35#define TEGRA_TMRUS_SIZE 0x1000
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]36
37/*******************************************************************************
38 * Tegra Clock and Reset Controller constants
39 ******************************************************************************/
40#define TEGRA_CAR_RESET_BASE 0x60006000
41
42/*******************************************************************************
43 * Tegra Flow Controller constants
44 ******************************************************************************/
45#define TEGRA_FLOWCTRL_BASE 0x60007000
46
47/*******************************************************************************
48 * Tegra Secure Boot Controller constants
49 ******************************************************************************/
50#define TEGRA_SB_BASE 0x6000C200
51
52/*******************************************************************************
53 * Tegra Exception Vectors constants
54 ******************************************************************************/
55#define TEGRA_EVP_BASE 0x6000F000
56
57/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]58 * Tegra Miscellaneous register constants
59 ******************************************************************************/
60#define TEGRA_MISC_BASE 0x70000000
61#define HARDWARE_REVISION_OFFSET 0x804
62
63/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]64 * Tegra UART controller base addresses
65 ******************************************************************************/
66#define TEGRA_UARTA_BASE 0x70006000
67#define TEGRA_UARTB_BASE 0x70006040
68#define TEGRA_UARTC_BASE 0x70006200
69#define TEGRA_UARTD_BASE 0x70006300
70#define TEGRA_UARTE_BASE 0x70006400
71
72/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]73 * Tegra Power Mgmt Controller constants
74 ******************************************************************************/
75#define TEGRA_PMC_BASE 0x7000E400
76
77/*******************************************************************************
78 * Tegra Memory Controller constants
79 ******************************************************************************/
80#define TEGRA_MC_BASE 0x70019000
81
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]82/* TZDRAM carveout configuration registers */
83#define MC_SECURITY_CFG0_0 0x70
84#define MC_SECURITY_CFG1_0 0x74
85#define MC_SECURITY_CFG3_0 0x9BC
86
87/* Video Memory carveout configuration registers */
88#define MC_VIDEO_PROTECT_BASE_HI 0x978
89#define MC_VIDEO_PROTECT_BASE_LO 0x648
90#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
91
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]92/*******************************************************************************
93 * Tegra TZRAM constants
94 ******************************************************************************/
95#define TEGRA_TZRAM_BASE 0x7C010000
96#define TEGRA_TZRAM_SIZE 0x10000
97
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]98#endif /* __TEGRA_DEF_H__ */