Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <assert.h> |
| 33 | #include <bl31.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <cci400.h> |
| 36 | #include <console.h> |
| 37 | #include <mmio.h> |
| 38 | #include <platform.h> |
| 39 | #include <stddef.h> |
| 40 | #include "juno_def.h" |
| 41 | #include "juno_private.h" |
| 42 | #include "mhu.h" |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * Declarations of linker defined symbols which will help us find the layout |
| 46 | * of trusted RAM |
| 47 | ******************************************************************************/ |
| 48 | extern unsigned long __RO_START__; |
| 49 | extern unsigned long __RO_END__; |
| 50 | |
| 51 | extern unsigned long __COHERENT_RAM_START__; |
| 52 | extern unsigned long __COHERENT_RAM_END__; |
| 53 | |
| 54 | /* |
| 55 | * The next 2 constants identify the extents of the code & RO data region. |
| 56 | * These addresses are used by the MMU setup code and therefore they must be |
| 57 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 58 | * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. |
| 59 | */ |
| 60 | #define BL31_RO_BASE (unsigned long)(&__RO_START__) |
| 61 | #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) |
| 62 | |
| 63 | /* |
| 64 | * The next 2 constants identify the extents of the coherent memory region. |
| 65 | * These addresses are used by the MMU setup code and therefore they must be |
| 66 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 67 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols |
| 68 | * refer to page-aligned addresses. |
| 69 | */ |
| 70 | #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 71 | #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| 72 | |
| 73 | /****************************************************************************** |
| 74 | * Placeholder variables for copying the arguments that have been passed to |
| 75 | * BL3-1 from BL2. |
| 76 | ******************************************************************************/ |
| 77 | static entry_point_info_t bl32_ep_info; |
| 78 | static entry_point_info_t bl33_ep_info; |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 82 | * the security state specified. BL3-3 corresponds to the non-secure image type |
| 83 | * while BL3-2 corresponds to the secure image type. A NULL pointer is returned |
| 84 | * if the image does not exist. |
| 85 | ******************************************************************************/ |
| 86 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 87 | { |
| 88 | entry_point_info_t *next_image_info; |
| 89 | |
| 90 | next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; |
| 91 | |
| 92 | /* None of the images on this platform can have 0x0 as the entrypoint */ |
| 93 | if (next_image_info->pc) |
| 94 | return next_image_info; |
| 95 | else |
| 96 | return NULL; |
| 97 | } |
| 98 | |
| 99 | /******************************************************************************* |
| 100 | * Perform any BL3-1 specific platform actions. Here is an opportunity to copy |
| 101 | * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they |
| 102 | * are lost (potentially). This needs to be done before the MMU is initialized |
| 103 | * so that the memory layout can be used while creating page tables. Also, BL2 |
| 104 | * has flushed this information to memory, so we are guaranteed to pick up good |
| 105 | * data |
| 106 | ******************************************************************************/ |
| 107 | void bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 108 | void *plat_params_from_bl2) |
| 109 | { |
| 110 | /* Initialize the console to provide early debug support */ |
| 111 | console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); |
| 112 | |
| 113 | /* |
| 114 | * Initialise the CCI-400 driver for BL31 so that it is accessible after |
| 115 | * a warm boot. BL1 should have already enabled CCI coherency for this |
| 116 | * cluster during cold boot. |
| 117 | */ |
| 118 | cci_init(CCI400_BASE, |
| 119 | CCI400_SL_IFACE3_CLUSTER_IX, |
| 120 | CCI400_SL_IFACE4_CLUSTER_IX); |
| 121 | |
| 122 | /* |
| 123 | * Check params passed from BL2 should not be NULL, |
| 124 | */ |
| 125 | assert(from_bl2 != NULL); |
| 126 | assert(from_bl2->h.type == PARAM_BL31); |
| 127 | assert(from_bl2->h.version >= VERSION_1); |
| 128 | /* |
| 129 | * In debug builds, we pass a special value in 'plat_params_from_bl2' |
| 130 | * to verify platform parameters from BL2 to BL3-1. |
| 131 | * In release builds, it's not used. |
| 132 | */ |
| 133 | assert(((unsigned long long)plat_params_from_bl2) == |
| 134 | JUNO_BL31_PLAT_PARAM_VAL); |
| 135 | |
| 136 | /* |
| 137 | * Copy BL3-2 and BL3-3 entry point information. |
| 138 | * They are stored in Secure RAM, in BL2's address space. |
| 139 | */ |
| 140 | bl32_ep_info = *from_bl2->bl32_ep_info; |
| 141 | bl33_ep_info = *from_bl2->bl33_ep_info; |
| 142 | } |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * Initialize the MHU and the GIC. |
| 146 | ******************************************************************************/ |
| 147 | void bl31_platform_setup(void) |
| 148 | { |
| 149 | unsigned int reg_val; |
| 150 | |
| 151 | mhu_secure_init(); |
| 152 | |
| 153 | /* Initialize the gic cpu and distributor interfaces */ |
| 154 | gic_setup(); |
| 155 | |
| 156 | /* Enable and initialize the System level generic timer */ |
| 157 | mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); |
| 158 | |
| 159 | /* Allow access to the System counter timer module */ |
| 160 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 161 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 162 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 163 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| 164 | |
| 165 | reg_val = (1 << CNTNSAR_NS_SHIFT(1)); |
| 166 | mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 167 | |
| 168 | /* Topologies are best known to the platform. */ |
| 169 | plat_setup_topology(); |
| 170 | } |
| 171 | |
| 172 | /******************************************************************************* |
| 173 | * Perform the very early platform specific architectural setup here. At the |
| 174 | * moment this is only intializes the mmu in a quick and dirty way. |
| 175 | ******************************************************************************/ |
| 176 | void bl31_plat_arch_setup() |
| 177 | { |
| 178 | configure_mmu_el3(BL31_RO_BASE, |
| 179 | BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, |
| 180 | BL31_RO_BASE, |
| 181 | BL31_RO_LIMIT, |
| 182 | BL31_COHERENT_RAM_BASE, |
| 183 | BL31_COHERENT_RAM_LIMIT); |
| 184 | } |