| Jit Loon Lim | 8bb9193 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef AGX5_PINMUX_H |
| 8 | #define AGX5_PINMUX_H |
| 9 | |
| 10 | /* PINMUX REGISTER ADDRESS */ |
| 11 | #define AGX5_PINMUX_PIN0SEL 0x10d13000 |
| 12 | #define AGX5_PINMUX_IO0CTRL 0x10d13130 |
| 13 | #define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300 |
| 14 | #define AGX5_PINMUX_IO0_DELAY 0x10d13400 |
| 15 | #define AGX5_PERIPHERAL 0x10d14044 |
| 16 | |
| 17 | #include "socfpga_handoff.h" |
| 18 | |
| 19 | /* PINMUX DEFINE */ |
| 20 | #define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
| 21 | #define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec |
| 22 | #define PINMUX_HANDOFF_CONFIG_VAL 0x7e000 |
| 23 | |
| 24 | /* Macros */ |
| 25 | #define SOCFPGA_PINMUX_SEL_NAND (0x03) |
| 26 | #define SOCFPGA_PINMUX_PIN0SEL (0x00) |
| 27 | #define SOCFPGA_PINMUX_PIN1SEL (0x04) |
| 28 | #define SOCFPGA_PINMUX_PIN2SEL (0x08) |
| 29 | #define SOCFPGA_PINMUX_PIN3SEL (0x0C) |
| 30 | #define SOCFPGA_PINMUX_PIN4SEL (0x10) |
| 31 | #define SOCFPGA_PINMUX_PIN5SEL (0x14) |
| 32 | #define SOCFPGA_PINMUX_PIN6SEL (0x18) |
| 33 | #define SOCFPGA_PINMUX_PIN7SEL (0x1C) |
| 34 | #define SOCFPGA_PINMUX_PIN8SEL (0x20) |
| 35 | #define SOCFPGA_PINMUX_PIN9SEL (0x24) |
| 36 | #define SOCFPGA_PINMUX_PIN10SEL (0x28) |
| 37 | #define SOCFPGA_PINMUX_PIN11SEL (0x2C) |
| 38 | #define SOCFPGA_PINMUX_PIN12SEL (0x30) |
| 39 | #define SOCFPGA_PINMUX_PIN13SEL (0x34) |
| 40 | #define SOCFPGA_PINMUX_PIN14SEL (0x38) |
| 41 | #define SOCFPGA_PINMUX_PIN15SEL (0x3C) |
| 42 | #define SOCFPGA_PINMUX_PIN16SEL (0x40) |
| 43 | #define SOCFPGA_PINMUX_PIN17SEL (0x44) |
| 44 | #define SOCFPGA_PINMUX_PIN18SEL (0x48) |
| 45 | #define SOCFPGA_PINMUX_PIN19SEL (0x4C) |
| 46 | #define SOCFPGA_PINMUX_PIN20SEL (0x50) |
| 47 | #define SOCFPGA_PINMUX_PIN21SEL (0x54) |
| 48 | #define SOCFPGA_PINMUX_PIN22SEL (0x58) |
| 49 | #define SOCFPGA_PINMUX_PIN23SEL (0x5C) |
| 50 | #define SOCFPGA_PINMUX_PIN24SEL (0x60) |
| 51 | #define SOCFPGA_PINMUX_PIN25SEL (0x64) |
| 52 | #define SOCFPGA_PINMUX_PIN26SEL (0x68) |
| 53 | #define SOCFPGA_PINMUX_PIN27SEL (0x6C) |
| 54 | #define SOCFPGA_PINMUX_PIN28SEL (0x70) |
| 55 | #define SOCFPGA_PINMUX_PIN29SEL (0x74) |
| 56 | #define SOCFPGA_PINMUX_PIN30SEL (0x78) |
| 57 | #define SOCFPGA_PINMUX_PIN31SEL (0x7C) |
| 58 | #define SOCFPGA_PINMUX_PIN32SEL (0x80) |
| 59 | #define SOCFPGA_PINMUX_PIN33SEL (0x84) |
| 60 | #define SOCFPGA_PINMUX_PIN34SEL (0x88) |
| 61 | #define SOCFPGA_PINMUX_PIN35SEL (0x8C) |
| 62 | #define SOCFPGA_PINMUX_PIN36SEL (0x90) |
| 63 | #define SOCFPGA_PINMUX_PIN37SEL (0x94) |
| 64 | #define SOCFPGA_PINMUX_PIN38SEL (0x98) |
| 65 | #define SOCFPGA_PINMUX_PIN39SEL (0x9C) |
| 66 | #define SOCFPGA_PINMUX_PIN40SEL (0x100) |
| 67 | #define SOCFPGA_PINMUX_PIN41SEL (0x104) |
| 68 | #define SOCFPGA_PINMUX_PIN42SEL (0x108) |
| 69 | #define SOCFPGA_PINMUX_PIN43SEL (0x10C) |
| 70 | #define SOCFPGA_PINMUX_PIN44SEL (0x110) |
| 71 | #define SOCFPGA_PINMUX_PIN45SEL (0x114) |
| 72 | #define SOCFPGA_PINMUX_PIN46SEL (0x118) |
| 73 | #define SOCFPGA_PINMUX_PIN47SEL (0x11C) |
| 74 | |
| 75 | #define SOCFPGA_PINMUX_IO0CTRL (0x00) |
| 76 | #define SOCFPGA_PINMUX_IO1CTRL (0x04) |
| 77 | #define SOCFPGA_PINMUX_IO2CTRL (0x08) |
| 78 | #define SOCFPGA_PINMUX_IO3CTRL (0x0C) |
| 79 | #define SOCFPGA_PINMUX_IO4CTRL (0x10) |
| 80 | #define SOCFPGA_PINMUX_IO5CTRL (0x14) |
| 81 | #define SOCFPGA_PINMUX_IO6CTRL (0x18) |
| 82 | #define SOCFPGA_PINMUX_IO7CTRL (0x1C) |
| 83 | #define SOCFPGA_PINMUX_IO8CTRL (0x20) |
| 84 | #define SOCFPGA_PINMUX_IO9CTRL (0x24) |
| 85 | #define SOCFPGA_PINMUX_IO10CTRL (0x28) |
| 86 | #define SOCFPGA_PINMUX_IO11CTRL (0x2C) |
| 87 | #define SOCFPGA_PINMUX_IO12CTRL (0x30) |
| 88 | #define SOCFPGA_PINMUX_IO13CTRL (0x34) |
| 89 | #define SOCFPGA_PINMUX_IO14CTRL (0x38) |
| 90 | #define SOCFPGA_PINMUX_IO15CTRL (0x3C) |
| 91 | #define SOCFPGA_PINMUX_IO16CTRL (0x40) |
| 92 | #define SOCFPGA_PINMUX_IO17CTRL (0x44) |
| 93 | #define SOCFPGA_PINMUX_IO18CTRL (0x48) |
| 94 | #define SOCFPGA_PINMUX_IO19CTRL (0x4C) |
| 95 | #define SOCFPGA_PINMUX_IO20CTRL (0x50) |
| 96 | #define SOCFPGA_PINMUX_IO21CTRL (0x54) |
| 97 | #define SOCFPGA_PINMUX_IO22CTRL (0x58) |
| 98 | #define SOCFPGA_PINMUX_IO23CTRL (0x5C) |
| 99 | #define SOCFPGA_PINMUX_IO24CTRL (0x60) |
| 100 | #define SOCFPGA_PINMUX_IO25CTRL (0x64) |
| 101 | #define SOCFPGA_PINMUX_IO26CTRL (0x68) |
| 102 | #define SOCFPGA_PINMUX_IO27CTRL (0x6C) |
| 103 | #define SOCFPGA_PINMUX_IO28CTRL (0xD0) |
| 104 | #define SOCFPGA_PINMUX_IO29CTRL (0xD4) |
| 105 | #define SOCFPGA_PINMUX_IO30CTRL (0xD8) |
| 106 | #define SOCFPGA_PINMUX_IO31CTRL (0xDC) |
| 107 | #define SOCFPGA_PINMUX_IO32CTRL (0xE0) |
| 108 | #define SOCFPGA_PINMUX_IO33CTRL (0xE4) |
| 109 | #define SOCFPGA_PINMUX_IO34CTRL (0xE8) |
| 110 | #define SOCFPGA_PINMUX_IO35CTRL (0xEC) |
| 111 | #define SOCFPGA_PINMUX_IO36CTRL (0xF0) |
| 112 | #define SOCFPGA_PINMUX_IO37CTRL (0xF4) |
| 113 | #define SOCFPGA_PINMUX_IO38CTRL (0xF8) |
| 114 | #define SOCFPGA_PINMUX_IO39CTRL (0xFC) |
| 115 | #define SOCFPGA_PINMUX_IO40CTRL (0x100) |
| 116 | #define SOCFPGA_PINMUX_IO41CTRL (0x104) |
| 117 | #define SOCFPGA_PINMUX_IO42CTRL (0x108) |
| 118 | #define SOCFPGA_PINMUX_IO43CTRL (0x10C) |
| 119 | #define SOCFPGA_PINMUX_IO44CTRL (0x110) |
| 120 | #define SOCFPGA_PINMUX_IO45CTRL (0x114) |
| 121 | #define SOCFPGA_PINMUX_IO46CTRL (0x118) |
| 122 | #define SOCFPGA_PINMUX_IO47CTRL (0x11C) |
| 123 | |
| 124 | #define SOCFPGA_PINMUX_EMAC0_USEFPGA (0x00) |
| 125 | #define SOCFPGA_PINMUX_EMAC1_USEFPGA (0x04) |
| 126 | #define SOCFPGA_PINMUX_EMAC2_USEFPGA (0x08) |
| 127 | #define SOCFPGA_PINMUX_I2C0_USEFPGA (0x0C) |
| 128 | #define SOCFPGA_PINMUX_I2C1_USEFPGA (0x10) |
| 129 | #define SOCFPGA_PINMUX_I2C_EMAC0_USEFPGA (0x14) |
| 130 | #define SOCFPGA_PINMUX_I2C_EMAC1_USEFPGA (0x18) |
| 131 | #define SOCFPGA_PINMUX_I2C_EMAC2_USEFPGA (0x1C) |
| 132 | #define SOCFPGA_PINMUX_NAND_USEFPGA (0x20) |
| 133 | #define SOCFPGA_PINMUX_SPIM0_USEFPGA (0x28) |
| 134 | #define SOCFPGA_PINMUX_SPIM1_USEFPGA (0x2C) |
| 135 | #define SOCFPGA_PINMUX_SPIS0_USEFPGA (0x30) |
| 136 | #define SOCFPGA_PINMUX_SPIS1_USEFPGA (0x34) |
| 137 | #define SOCFPGA_PINMUX_UART0_USEFPGA (0x38) |
| 138 | #define SOCFPGA_PINMUX_UART1_USEFPGA (0x3C) |
| 139 | #define SOCFPGA_PINMUX_MDIO0_USEFPGA (0x40) |
| 140 | #define SOCFPGA_PINMUX_MDIO1_USEFPGA (0x44) |
| 141 | #define SOCFPGA_PINMUX_MDIO2_USEFPGA (0x48) |
| 142 | #define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50) |
| 143 | #define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54) |
| 144 | |
| 145 | #define SOCFPGA_PINMUX_IO0DELAY (0x00) |
| 146 | #define SOCFPGA_PINMUX_IO1DELAY (0x04) |
| 147 | #define SOCFPGA_PINMUX_IO2DELAY (0x08) |
| 148 | #define SOCFPGA_PINMUX_IO3DELAY (0x0C) |
| 149 | #define SOCFPGA_PINMUX_IO4DELAY (0x10) |
| 150 | #define SOCFPGA_PINMUX_IO5DELAY (0x14) |
| 151 | #define SOCFPGA_PINMUX_IO6DELAY (0x18) |
| 152 | #define SOCFPGA_PINMUX_IO7DELAY (0x1C) |
| 153 | #define SOCFPGA_PINMUX_IO8DELAY (0x20) |
| 154 | #define SOCFPGA_PINMUX_IO9DELAY (0x24) |
| 155 | #define SOCFPGA_PINMUX_IO10DELAY (0x28) |
| 156 | #define SOCFPGA_PINMUX_IO11DELAY (0x2C) |
| 157 | #define SOCFPGA_PINMUX_IO12DELAY (0x30) |
| 158 | #define SOCFPGA_PINMUX_IO13DELAY (0x34) |
| 159 | #define SOCFPGA_PINMUX_IO14DELAY (0x38) |
| 160 | #define SOCFPGA_PINMUX_IO15DELAY (0x3C) |
| 161 | #define SOCFPGA_PINMUX_IO16DELAY (0x40) |
| 162 | #define SOCFPGA_PINMUX_IO17DELAY (0x44) |
| 163 | #define SOCFPGA_PINMUX_IO18DELAY (0x48) |
| 164 | #define SOCFPGA_PINMUX_IO19DELAY (0x4C) |
| 165 | #define SOCFPGA_PINMUX_IO20DELAY (0x50) |
| 166 | #define SOCFPGA_PINMUX_IO21DELAY (0x54) |
| 167 | #define SOCFPGA_PINMUX_IO22DELAY (0x58) |
| 168 | #define SOCFPGA_PINMUX_IO23DELAY (0x5C) |
| 169 | #define SOCFPGA_PINMUX_IO24DELAY (0x60) |
| 170 | #define SOCFPGA_PINMUX_IO25DELAY (0x64) |
| 171 | #define SOCFPGA_PINMUX_IO26DELAY (0x68) |
| 172 | #define SOCFPGA_PINMUX_IO27DELAY (0x6C) |
| 173 | #define SOCFPGA_PINMUX_IO28DELAY (0x70) |
| 174 | #define SOCFPGA_PINMUX_IO29DELAY (0x74) |
| 175 | #define SOCFPGA_PINMUX_IO30DELAY (0x78) |
| 176 | #define SOCFPGA_PINMUX_IO31DELAY (0x7C) |
| 177 | #define SOCFPGA_PINMUX_IO32DELAY (0x80) |
| 178 | #define SOCFPGA_PINMUX_IO33DELAY (0x84) |
| 179 | #define SOCFPGA_PINMUX_IO34DELAY (0x88) |
| 180 | #define SOCFPGA_PINMUX_IO35DELAY (0x8C) |
| 181 | #define SOCFPGA_PINMUX_IO36DELAY (0x90) |
| 182 | #define SOCFPGA_PINMUX_IO37DELAY (0x94) |
| 183 | #define SOCFPGA_PINMUX_IO38DELAY (0x98) |
| 184 | #define SOCFPGA_PINMUX_IO39DELAY (0x9C) |
| 185 | #define SOCFPGA_PINMUX_IO40DELAY (0xA0) |
| 186 | #define SOCFPGA_PINMUX_IO41DELAY (0xA4) |
| 187 | #define SOCFPGA_PINMUX_IO42DELAY (0xA8) |
| 188 | #define SOCFPGA_PINMUX_IO43DELAY (0xAC) |
| 189 | #define SOCFPGA_PINMUX_IO44DELAY (0xB0) |
| 190 | #define SOCFPGA_PINMUX_IO45DELAY (0xB4) |
| 191 | #define SOCFPGA_PINMUX_IO46DELAY (0xB8) |
| 192 | #define SOCFPGA_PINMUX_IO47DELAY (0xBC) |
| 193 | |
| 194 | #define SOCFPGA_PINMUX_I3C0_USEFPGA (0xC0) |
| 195 | #define SOCFPGA_PINMUX_I3C1_USEFPGA (0xC4) |
| 196 | |
| 197 | #define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \ |
| 198 | + (SOCFPGA_PINMUX_##_reg)) |
| 199 | |
| 200 | void config_pinmux(handoff *handoff); |
| 201 | void config_peripheral(handoff *handoff); |
| 202 | #endif |