Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 1 | /* |
Tamas Ban | f728b61 | 2023-05-08 13:50:37 +0200 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <plat/arm/board/common/v2m_def.h> |
| 11 | #include <plat/arm/common/arm_def.h> |
| 12 | #include <plat/arm/css/common/css_def.h> |
| 13 | |
| 14 | /* UART related constants */ |
| 15 | #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000) |
| 16 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ U(50000000) |
| 17 | |
Chandni Cherukuri | 118ad71 | 2021-12-02 11:22:59 +0530 | [diff] [blame] | 18 | /* IOFPGA UART0 */ |
| 19 | #define PLAT_ARM_RUN_UART_BASE ULL(0x1C090000) |
| 20 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ U(24000000) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 21 | |
| 22 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 23 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
| 24 | |
| 25 | #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) |
| 26 | #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) |
| 27 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 28 | #define MAX_IO_DEVICES U(3) |
| 29 | #define MAX_IO_HANDLES U(4) |
| 30 | |
| 31 | #define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000) |
| 32 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE ULL(0x01000000) |
| 33 | |
| 34 | #define PLAT_ARM_NVM_BASE ULL(0x1A000000) |
| 35 | #define PLAT_ARM_NVM_SIZE ULL(0x01000000) |
| 36 | |
| 37 | #if defined NS_BL1U_BASE |
| 38 | #undef NS_BL1U_BASE |
| 39 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) |
| 40 | #endif |
| 41 | |
| 42 | /* |
| 43 | * There are no non-volatile counters in morello, these macros points |
| 44 | * to unused addresses. |
| 45 | */ |
| 46 | #define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000) |
| 47 | #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0000)) |
| 48 | #define TFW_NVCTR_SIZE U(4) |
| 49 | #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0004)) |
| 50 | #define NTFW_CTR_SIZE U(4) |
| 51 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 52 | /* |
| 53 | * To access the complete DDR memory along with remote chip's DDR memory, |
| 54 | * which is at 4 TB offset, physical and virtual address space limits are |
| 55 | * extended to 43-bits. |
| 56 | */ |
| 57 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) |
| 58 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) |
| 59 | |
| 60 | #if CSS_USE_SCMI_SDS_DRIVER |
| 61 | #define MORELLO_SCMI_PAYLOAD_BASE ULL(0x45400000) |
Tamas Ban | f728b61 | 2023-05-08 13:50:37 +0200 | [diff] [blame] | 62 | /* |
| 63 | * Index of SDS region used in the communication with SCP |
| 64 | */ |
| 65 | #define SDS_SCP_AP_REGION_ID U(0) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 66 | #else |
| 67 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE ULL(0x45400000) |
| 68 | #endif |
| 69 | |
| 70 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 71 | |
| 72 | /* |
| 73 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 74 | * plus a little space for growth. |
| 75 | */ |
| 76 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) |
| 77 | |
| 78 | /* |
| 79 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 80 | */ |
| 81 | |
| 82 | #if USE_ROMLIB |
| 83 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 84 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000) |
| 85 | #else |
| 86 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) |
| 87 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) |
| 88 | #endif |
| 89 | |
| 90 | /* |
| 91 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 92 | * little space for growth. |
| 93 | */ |
| 94 | #if TRUSTED_BOARD_BOOT |
| 95 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
| 96 | #else |
| 97 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x14000) |
| 98 | #endif |
| 99 | |
| 100 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 101 | |
| 102 | /******************************************************************************* |
| 103 | * MORELLO topology related constants |
| 104 | ******************************************************************************/ |
| 105 | #define MORELLO_MAX_CPUS_PER_CLUSTER U(2) |
| 106 | #define PLAT_ARM_CLUSTER_COUNT U(2) |
| 107 | #define PLAT_MORELLO_CHIP_COUNT U(1) |
| 108 | #define MORELLO_MAX_CLUSTERS_PER_CHIP U(2) |
| 109 | #define MORELLO_MAX_PE_PER_CPU U(1) |
| 110 | |
| 111 | #define PLATFORM_CORE_COUNT (PLAT_MORELLO_CHIP_COUNT * \ |
| 112 | PLAT_ARM_CLUSTER_COUNT * \ |
| 113 | MORELLO_MAX_CPUS_PER_CLUSTER * \ |
| 114 | MORELLO_MAX_PE_PER_CPU) |
| 115 | |
| 116 | /* System power domain level */ |
| 117 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 |
| 118 | |
| 119 | /* |
| 120 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 121 | * plat_arm_mmap array defined for each BL stage. |
| 122 | */ |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 123 | #if IMAGE_BL1 || IMAGE_BL31 |
| 124 | # define PLAT_ARM_MMAP_ENTRIES U(6) |
| 125 | # define MAX_XLAT_TABLES U(7) |
| 126 | #else |
| 127 | # define PLAT_ARM_MMAP_ENTRIES U(5) |
| 128 | # define MAX_XLAT_TABLES U(6) |
| 129 | #endif |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 130 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 131 | /* |
| 132 | * Size of cacheable stacks |
| 133 | */ |
| 134 | #if defined(IMAGE_BL1) |
| 135 | # if TRUSTED_BOARD_BOOT |
| 136 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 137 | # else |
| 138 | # define PLATFORM_STACK_SIZE UL(0x440) |
| 139 | # endif |
| 140 | #elif defined(IMAGE_BL2) |
| 141 | # if TRUSTED_BOARD_BOOT |
| 142 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 143 | # else |
| 144 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 145 | # endif |
| 146 | #elif defined(IMAGE_BL2U) |
| 147 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 148 | #elif defined(IMAGE_BL31) |
| 149 | # if SPM_MM |
| 150 | # define PLATFORM_STACK_SIZE UL(0x500) |
| 151 | # else |
| 152 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 153 | # endif |
| 154 | #elif defined(IMAGE_BL32) |
| 155 | # define PLATFORM_STACK_SIZE UL(0x440) |
| 156 | #endif |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 157 | |
| 158 | #define PLAT_ARM_NSTIMER_FRAME_ID U(0) |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 159 | |
| 160 | #define PLAT_ARM_TRUSTED_ROM_BASE U(0x0) |
| 161 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) /* 128KB */ |
| 162 | |
| 163 | #define PLAT_ARM_NSRAM_BASE ULL(0x06000000) |
| 164 | #define PLAT_ARM_NSRAM_SIZE UL(0x00010000) /* 64KB */ |
| 165 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 166 | #define PLAT_CSS_MHU_BASE UL(0x45000000) |
| 167 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 168 | #define PLAT_MAX_PWR_LVL U(2) |
| 169 | |
Werner Lewis | 395a4fa | 2023-05-25 15:24:46 +0100 | [diff] [blame] | 170 | /* Interrupt handling constants */ |
| 171 | #define MORELLO_IRQ_SEC_UART U(87) |
| 172 | #define MORELLO_IRQ_DISPLAY_TCU_EVENT_Q U(107) |
| 173 | #define MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC U(111) |
| 174 | #define MORELLO_IRQ_DISPLAY_TCU_GLOBAL U(113) |
| 175 | #define MORELLO_IRQ_MMU_TCU1_EVENT_Q U(257) |
| 176 | #define MORELLO_IRQ_MMU_TCU1_CMD_SYNC U(258) |
| 177 | #define MORELLO_IRQ_MMU_TCU1_GLOBAL U(259) |
| 178 | #define MORELLO_IRQ_MMU_TCU2_EVENT_Q U(264) |
| 179 | #define MORELLO_IRQ_MMU_TCU2_CMD_SYNC U(265) |
| 180 | #define MORELLO_IRQ_MMU_TCU2_GLOBAL U(266) |
| 181 | #define MORELLO_IRQ_CLUSTER0_MHU U(349) |
| 182 | #define MORELLO_IRQ_CLUSTER1_MHU U(351) |
| 183 | #define MORELLO_IRQ_P0_REFCLK U(412) |
| 184 | #define MORELLO_IRQ_P1_REFCLK U(413) |
| 185 | |
| 186 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 187 | ARM_G1S_IRQ_PROPS(grp), \ |
| 188 | INTR_PROP_DESC(CSS_IRQ_MHU, \ |
| 189 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 190 | INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ |
| 191 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 192 | INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ |
| 193 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 194 | INTR_PROP_DESC(MORELLO_IRQ_SEC_UART, \ |
| 195 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 196 | INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_EVENT_Q, \ |
| 197 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 198 | INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC, \ |
| 199 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 200 | INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_GLOBAL, \ |
| 201 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 202 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_EVENT_Q, \ |
| 203 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 204 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_CMD_SYNC, \ |
| 205 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 206 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_GLOBAL, \ |
| 207 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 208 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_EVENT_Q, \ |
| 209 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 210 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_CMD_SYNC, \ |
| 211 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 212 | INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_GLOBAL, \ |
| 213 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 214 | INTR_PROP_DESC(MORELLO_IRQ_CLUSTER0_MHU, \ |
| 215 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 216 | INTR_PROP_DESC(MORELLO_IRQ_CLUSTER1_MHU, \ |
| 217 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 218 | INTR_PROP_DESC(MORELLO_IRQ_P0_REFCLK, \ |
| 219 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 220 | INTR_PROP_DESC(MORELLO_IRQ_P1_REFCLK, \ |
| 221 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) |
| 222 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 223 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 224 | |
| 225 | #define MORELLO_DEVICE_BASE ULL(0x08000000) |
| 226 | #define MORELLO_DEVICE_SIZE ULL(0x48000000) |
| 227 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 228 | /*Secure Watchdog Constants */ |
| 229 | #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) |
| 230 | #define SBSA_SECURE_WDOG_TIMEOUT UL(1000) |
| 231 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 232 | #define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \ |
| 233 | MORELLO_DEVICE_BASE, \ |
| 234 | MORELLO_DEVICE_SIZE, \ |
| 235 | MT_DEVICE | MT_RW | MT_SECURE) |
| 236 | |
| 237 | #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ |
| 238 | ARM_DRAM1_BASE, \ |
| 239 | ARM_DRAM1_SIZE, \ |
| 240 | MT_MEMORY | MT_RW | MT_NS) |
| 241 | |
| 242 | /* GIC related constants */ |
| 243 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 244 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 245 | #define PLAT_ARM_GICR_BASE UL(0x300C0000) |
| 246 | |
Chandni Cherukuri | c5a0c37 | 2020-10-01 10:11:44 +0530 | [diff] [blame] | 247 | /* Number of SCMI channels on the platform */ |
| 248 | #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) |
| 249 | |
Chandni Cherukuri | c873efc | 2023-02-16 20:22:32 +0530 | [diff] [blame] | 250 | /* Platform ID address */ |
| 251 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
| 252 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 253 | #endif /* PLATFORM_DEF_H */ |