blob: 955c530e83fedfca00c159368ff45f099f68e36d [file] [log] [blame]
Chris Kay03be39d2021-05-05 13:38:30 +01001/*
2 * Copyright (c) 2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MPMM_H
8#define MPMM_H
9
10#include <stdbool.h>
11
12#include <platform_def.h>
13
14/*
15 * Enable the Maximum Power Mitigation Mechanism.
16 *
17 * This function will enable MPMM for the current core. The AMU counters
18 * representing the MPMM gears must have been configured and enabled prior to
19 * calling this function.
20 */
21void mpmm_enable(void);
22
23/*
24 * MPMM core data.
25 *
26 * This structure represents per-core data retrieved from the hardware
27 * configuration device tree.
28 */
29struct mpmm_core {
30 /*
31 * Whether MPMM is supported.
32 *
33 * Cores with support for MPMM offer one or more auxiliary AMU counters
34 * representing MPMM gears.
35 */
36 bool supported;
37};
38
39/*
40 * MPMM topology.
41 *
42 * This topology structure describes the system-wide representation of the
43 * information retrieved from the hardware configuration device tree.
44 */
45struct mpmm_topology {
46 struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */
47};
48
49#if !ENABLE_MPMM_FCONF
50/*
51 * Retrieve the platform's MPMM topology. A `NULL` return value is treated as a
52 * non-fatal error, in which case MPMM will not be enabled for any core.
53 */
54const struct mpmm_topology *plat_mpmm_topology(void);
55#endif /* ENABLE_MPMM_FCONF */
56
57#endif /* MPMM_H */