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Julius Wernerb624ae02017-06-09 15:17:15 -07001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
Julius Wernerb624ae02017-06-09 15:17:15 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef COREBOOT_H
8#define COREBOOT_H
Julius Wernerb624ae02017-06-09 15:17:15 -07009
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010010#include <stdint.h>
Julius Wernerb624ae02017-06-09 15:17:15 -070011
12typedef struct {
13 uint32_t type; /* always 2 (memory-mapped) on ARM */
14 uint32_t baseaddr;
15 uint32_t baud;
16 uint32_t regwidth; /* in bytes, i.e. usually 4 */
17 uint32_t input_hertz;
18 uint32_t uart_pci_addr; /* unused on current ARM systems */
19} coreboot_serial_t;
20extern coreboot_serial_t coreboot_serial;
21
Julius Werner8acc4932020-03-26 18:06:21 -070022#define COREBOOT_MAX_MEMRANGES 32 /* libpayload also uses this limit */
23
24typedef struct __packed {
25 uint64_t start;
26 uint64_t size;
27 uint32_t type;
28} coreboot_memrange_t;
29extern coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
30
31typedef enum {
32 CB_MEM_NONE = 0, /* coreboot will never report this */
33 CB_MEM_RAM = 1,
34 CB_MEM_RESERVED = 2,
35 CB_MEM_ACPI = 3,
36 CB_MEM_NVS = 4,
37 CB_MEM_UNUSABLE = 5,
38 CB_MEM_VENDOR_RSVD = 6,
39 CB_MEM_TABLE = 16,
40} coreboot_memory_t;
41
Saurabh Gorecha86f7fb72020-10-15 00:05:36 +053042coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size);
Julius Wernerb624ae02017-06-09 15:17:15 -070043void coreboot_table_setup(void *base);
Jeffrey Kardatzke45521892023-02-09 10:45:35 -080044void coreboot_get_table_location(uint64_t *address, uint32_t *size);
Julius Wernerb624ae02017-06-09 15:17:15 -070045
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000046#endif /* COREBOOT_H */