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Yann Gautier7b7e4bf2019-01-17 19:16:03 +01001/*
Yann Gautier6fa04612021-05-25 18:14:24 +02002 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
Alexei Fedorov9fe73b22021-04-23 16:12:11 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
Yann Gautier7b7e4bf2019-01-17 19:16:03 +01006 * This header provides constants for the ARM GIC.
7 */
8
9#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
10#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
11
Yann Gautier6fa04612021-05-25 18:14:24 +020012#include <dt-bindings/interrupt-controller/irq.h>
13
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010014/* interrupt specifier cell 0 */
15
16#define GIC_SPI 0
17#define GIC_PPI 1
18
Alexei Fedorovcb8fef62021-04-12 12:49:54 +010019/*
20 * Interrupt specifier cell 2.
Yann Gautier6fa04612021-05-25 18:14:24 +020021 * The flags in irq.h are valid, plus those below.
Alexei Fedorovcb8fef62021-04-12 12:49:54 +010022 */
23#define GIC_CPU_MASK_RAW(x) ((x) << 8)
Yann Gautier6fa04612021-05-25 18:14:24 +020024#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
Alexei Fedorovcb8fef62021-04-12 12:49:54 +010025
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010026#endif