Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 1 | /* |
Daniel Boulby | 9460a23 | 2021-12-09 11:20:13 +0000 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SPMD_PRIVATE_H |
| 8 | #define SPMD_PRIVATE_H |
| 9 | |
| 10 | #include <context.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * Constants that allow assembler code to preserve callee-saved registers of the |
| 14 | * C runtime context while performing a security state switch. |
| 15 | ******************************************************************************/ |
| 16 | #define SPMD_C_RT_CTX_X19 0x0 |
| 17 | #define SPMD_C_RT_CTX_X20 0x8 |
| 18 | #define SPMD_C_RT_CTX_X21 0x10 |
| 19 | #define SPMD_C_RT_CTX_X22 0x18 |
| 20 | #define SPMD_C_RT_CTX_X23 0x20 |
| 21 | #define SPMD_C_RT_CTX_X24 0x28 |
| 22 | #define SPMD_C_RT_CTX_X25 0x30 |
| 23 | #define SPMD_C_RT_CTX_X26 0x38 |
| 24 | #define SPMD_C_RT_CTX_X27 0x40 |
| 25 | #define SPMD_C_RT_CTX_X28 0x48 |
| 26 | #define SPMD_C_RT_CTX_X29 0x50 |
| 27 | #define SPMD_C_RT_CTX_X30 0x58 |
| 28 | |
| 29 | #define SPMD_C_RT_CTX_SIZE 0x60 |
| 30 | #define SPMD_C_RT_CTX_ENTRIES (SPMD_C_RT_CTX_SIZE >> DWORD_SHIFT) |
| 31 | |
| 32 | #ifndef __ASSEMBLER__ |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 33 | #include <stdint.h> |
Olivier Deprez | 9afca12 | 2019-10-28 09:15:52 +0000 | [diff] [blame] | 34 | #include <lib/psci/psci_lib.h> |
| 35 | #include <plat/common/platform.h> |
| 36 | #include <services/ffa_svc.h> |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 37 | |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 38 | typedef enum spmc_state { |
| 39 | SPMC_STATE_RESET = 0, |
Olivier Deprez | 7c01633 | 2019-10-28 09:03:13 +0000 | [diff] [blame] | 40 | SPMC_STATE_OFF, |
| 41 | SPMC_STATE_ON_PENDING, |
| 42 | SPMC_STATE_ON |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 43 | } spmc_state_t; |
| 44 | |
| 45 | /* |
| 46 | * Data structure used by the SPM dispatcher (SPMD) in EL3 to track context of |
| 47 | * the SPM core (SPMC) at the next lower EL. |
| 48 | */ |
| 49 | typedef struct spmd_spm_core_context { |
| 50 | uint64_t c_rt_ctx; |
| 51 | cpu_context_t cpu_ctx; |
| 52 | spmc_state_t state; |
Olivier Deprez | a664c49 | 2020-08-05 11:27:42 +0200 | [diff] [blame] | 53 | bool secure_interrupt_ongoing; |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 54 | } spmd_spm_core_context_t; |
| 55 | |
| 56 | /* |
J-Alves | 2672cde | 2020-05-07 18:42:25 +0100 | [diff] [blame] | 57 | * Reserve ID for NS physical FFA Endpoint. |
Max Shvetsov | e79062e | 2020-03-12 15:16:40 +0000 | [diff] [blame] | 58 | */ |
Olivier Deprez | ebc3477 | 2020-04-16 16:59:21 +0200 | [diff] [blame] | 59 | #define FFA_NS_ENDPOINT_ID U(0) |
| 60 | |
| 61 | /* Mask and shift to check valid secure FF-A Endpoint ID. */ |
| 62 | #define SPMC_SECURE_ID_MASK U(1) |
| 63 | #define SPMC_SECURE_ID_SHIFT U(15) |
Max Shvetsov | e79062e | 2020-03-12 15:16:40 +0000 | [diff] [blame] | 64 | |
Olivier Deprez | ebc3477 | 2020-04-16 16:59:21 +0200 | [diff] [blame] | 65 | #define SPMD_DIRECT_MSG_ENDPOINT_ID U(FFA_ENDPOINT_ID_MAX - 1) |
Max Shvetsov | e79062e | 2020-03-12 15:16:40 +0000 | [diff] [blame] | 66 | |
Daniel Boulby | 9460a23 | 2021-12-09 11:20:13 +0000 | [diff] [blame] | 67 | /* Define SPMD target function IDs for framework messages to the SPMC */ |
| 68 | #define SPMD_FWK_MSG_BIT BIT(31) |
| 69 | #define SPMD_FWK_MSG_PSCI U(0) |
| 70 | #define SPMD_FWK_MSG_FFA_VERSION_REQ U(0x8) |
| 71 | #define SPMD_FWK_MSG_FFA_VERSION_RESP U(0x9) |
| 72 | |
| 73 | /* Function to build SPMD to SPMC message */ |
| 74 | void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target, |
| 75 | unsigned long long message); |
| 76 | |
Olivier Deprez | 2bae35f | 2020-04-16 13:39:06 +0200 | [diff] [blame] | 77 | /* Functions used to enter/exit SPMC synchronously */ |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 78 | uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx); |
| 79 | __dead2 void spmd_spm_core_sync_exit(uint64_t rc); |
| 80 | |
| 81 | /* Assembly helpers */ |
| 82 | uint64_t spmd_spm_core_enter(uint64_t *c_rt_ctx); |
| 83 | void __dead2 spmd_spm_core_exit(uint64_t c_rt_ctx, uint64_t ret); |
| 84 | |
Olivier Deprez | 9afca12 | 2019-10-28 09:15:52 +0000 | [diff] [blame] | 85 | /* SPMD SPD power management handlers */ |
| 86 | extern const spd_pm_ops_t spmd_pm; |
| 87 | |
Olivier Deprez | 87a9ee7 | 2019-10-28 08:52:45 +0000 | [diff] [blame] | 88 | /* SPMC entry point information helper */ |
| 89 | entry_point_info_t *spmd_spmc_ep_info_get(void); |
| 90 | |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 91 | /* SPMC ID getter */ |
| 92 | uint16_t spmd_spmc_id_get(void); |
| 93 | |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 94 | /* SPMC context on CPU based on mpidr */ |
| 95 | spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr); |
| 96 | |
Olivier Deprez | 2bae35f | 2020-04-16 13:39:06 +0200 | [diff] [blame] | 97 | /* SPMC context on current CPU get helper */ |
| 98 | spmd_spm_core_context_t *spmd_get_context(void); |
| 99 | |
Olivier Deprez | eae4596 | 2021-01-19 15:06:47 +0100 | [diff] [blame] | 100 | int spmd_pm_secondary_ep_register(uintptr_t entry_point); |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 101 | bool spmd_check_address_in_binary_image(uint64_t address); |
| 102 | |
Achin Gupta | 86f2353 | 2019-10-11 15:41:16 +0100 | [diff] [blame] | 103 | #endif /* __ASSEMBLER__ */ |
| 104 | |
| 105 | #endif /* SPMD_PRIVATE_H */ |