blob: 88f7397c6aebd05b7816cc6c7716b564654e9f32 [file] [log] [blame]
Etienne Carriere911de8c2018-02-02 13:23:22 +01001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Etienne Carriere911de8c2018-02-02 13:23:22 +01007#include <assert.h>
Etienne Carriere911de8c2018-02-02 13:23:22 +01008#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <drivers/arm/gic_common.h>
16#include <drivers/arm/gicv2.h>
17#include <drivers/console.h>
18#include <lib/mmio.h>
19#include <lib/xlat_tables/xlat_tables.h>
20#include <plat/common/platform.h>
21
Etienne Carriere911de8c2018-02-02 13:23:22 +010022#include "../qemu_private.h"
23
24#if RESET_TO_SP_MIN
25#error qemu does not support RESET_TO_SP_MIN
26#endif
27
28static entry_point_info_t bl33_image_ep_info;
29
Etienne Carriere911de8c2018-02-02 13:23:22 +010030/******************************************************************************
31 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
32 * interrupts.
33 *****************************************************************************/
34#define PLATFORM_G1S_PROPS(grp) \
35 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
36 grp, GIC_INTR_CFG_LEVEL), \
37 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
38 grp, GIC_INTR_CFG_LEVEL), \
39 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
40 grp, GIC_INTR_CFG_LEVEL), \
41 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
42 grp, GIC_INTR_CFG_LEVEL), \
43 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
44 grp, GIC_INTR_CFG_LEVEL), \
45 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
46 grp, GIC_INTR_CFG_LEVEL), \
47 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
48 grp, GIC_INTR_CFG_LEVEL), \
49 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
50 grp, GIC_INTR_CFG_LEVEL)
51
52#define PLATFORM_G0_PROPS(grp)
53
54static const interrupt_prop_t stih410_interrupt_props[] = {
55 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
56 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
57};
58
59static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
60
61static const struct gicv2_driver_data plat_gicv2_driver_data = {
62 .gicd_base = GICD_BASE,
63 .gicc_base = GICC_BASE,
64 .interrupt_props = stih410_interrupt_props,
65 .interrupt_props_num = ARRAY_SIZE(stih410_interrupt_props),
66 .target_masks = target_mask_array,
67 .target_masks_num = ARRAY_SIZE(target_mask_array),
68};
69
70/*******************************************************************************
71 * Return a pointer to the 'entry_point_info' structure of the next image for
72 * the security state specified. BL33 corresponds to the non-secure image type
73 * while BL32 corresponds to the secure image type. A NULL pointer is returned
74 * if the image does not exist.
75 ******************************************************************************/
76entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
77{
78 entry_point_info_t *next_image_info = &bl33_image_ep_info;
79
80 /*
81 * None of the images on the ARM development platforms can have 0x0
82 * as the entrypoint
83 */
84 if (next_image_info->pc)
85 return next_image_info;
86 else
87 return NULL;
88}
89
Antonio Nino Diaz099b0b12018-09-26 09:29:45 +010090void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
91 u_register_t arg2, u_register_t arg3)
Etienne Carriere911de8c2018-02-02 13:23:22 +010092{
Antonio Nino Diaz099b0b12018-09-26 09:29:45 +010093 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
Etienne Carriere911de8c2018-02-02 13:23:22 +010094
95 /* Initialize the console to provide early debug support */
96 console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
97 PLAT_QEMU_CONSOLE_BAUDRATE);
98
99 ERROR("qemu sp_min, console init\n");
100 /*
101 * Check params passed from BL2
102 */
103 assert(params_from_bl2);
104 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
105 assert(params_from_bl2->h.version >= VERSION_2);
106
107 bl_params_node_t *bl_params = params_from_bl2->head;
108
109 /*
110 * Copy BL33 entry point information from BL2's address space.
111 */
112 while (bl_params) {
113 if (bl_params->image_id == BL33_IMAGE_ID)
114 bl33_image_ep_info = *bl_params->ep_info;
115
116 bl_params = bl_params->next_params_info;
117 }
118
119 if (!bl33_image_ep_info.pc)
120 panic();
121}
122
123void sp_min_plat_arch_setup(void)
124{
Antonio Nino Diaz099b0b12018-09-26 09:29:45 +0100125 qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000126 BL_CODE_BASE, BL_CODE_END,
Etienne Carriere911de8c2018-02-02 13:23:22 +0100127 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
128
129}
130
131void sp_min_platform_setup(void)
132{
133 /* Initialize the gic cpu and distributor interfaces */
134 gicv2_driver_init(&plat_gicv2_driver_data);
135 gicv2_distif_init();
136 gicv2_pcpu_distif_init();
137 gicv2_cpuif_enable();
138}
139
140unsigned int plat_get_syscnt_freq2(void)
141{
142 return SYS_COUNTER_FREQ_IN_TICKS;
143}
144
145void sp_min_plat_fiq_handler(uint32_t id)
146{
147 VERBOSE("[sp_min] interrupt #%d\n", id);
148}