blob: 9478f321a20bdd7a5bf70404002d1853805f36de [file] [log] [blame]
Icenowy Zheng61da7562021-07-22 09:41:16 +08001/*
2 * Copyright (c) 2021 Sipeed
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SUNXI_CPUCFG_H
8#define SUNXI_CPUCFG_H
9
10#include <sunxi_mmap.h>
11
12/* c = cluster, n = core */
13#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
14#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
15#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
16#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
17
18#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
19#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
20#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
21#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
22
23#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
24#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
25#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
26 (c) * 0x10 + (n) * 4)
27
28#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
29#define SUNXI_AA64nAA32_OFFSET 4
30
31#endif /* SUNXI_CPUCFG_H */