Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Soby Mathew | 73b7bf9 | 2017-05-03 12:58:41 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 8 | #include <assert.h> |
Soby Mathew | 2f6cac4 | 2017-06-13 18:00:53 +0100 | [diff] [blame] | 9 | #include <cassert.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 10 | #include <css_def.h> |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 11 | #include <debug.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 12 | #include <platform.h> |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 13 | #include <stdint.h> |
Soby Mathew | 73b7bf9 | 2017-05-03 12:58:41 +0100 | [diff] [blame] | 14 | #include "../scpi/css_mhu.h" |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 15 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 16 | /* ID of the MHU slot used for the BOM protocol */ |
| 17 | #define BOM_MHU_SLOT_ID 0 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 18 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 19 | /* Boot commands sent from AP -> SCP */ |
| 20 | #define BOOT_CMD_INFO 0x00 |
| 21 | #define BOOT_CMD_DATA 0x01 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 22 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 23 | /* BOM command header */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 24 | typedef struct { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 25 | uint32_t id : 8; |
| 26 | uint32_t reserved : 24; |
| 27 | } bom_cmd_t; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 28 | |
| 29 | typedef struct { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 30 | uint32_t image_size; |
| 31 | uint32_t checksum; |
| 32 | } cmd_info_payload_t; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 33 | |
| 34 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 35 | * Unlike the SCPI protocol, the boot protocol uses the same memory region |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 36 | * for both AP -> SCP and SCP -> AP transfers; define the address of this... |
| 37 | */ |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 38 | #define BOM_SHARED_MEM PLAT_CSS_SCP_COM_SHARED_MEM_BASE |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 39 | #define BOM_CMD_HEADER ((bom_cmd_t *) BOM_SHARED_MEM) |
| 40 | #define BOM_CMD_PAYLOAD ((void *) (BOM_SHARED_MEM + sizeof(bom_cmd_t))) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 42 | typedef struct { |
| 43 | /* Offset from the base address of the Trusted RAM */ |
| 44 | uint32_t offset; |
| 45 | uint32_t block_size; |
| 46 | } cmd_data_payload_t; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 47 | |
Soby Mathew | 2f6cac4 | 2017-06-13 18:00:53 +0100 | [diff] [blame] | 48 | /* |
| 49 | * All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above |
| 50 | * BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is |
| 51 | * set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor |
| 52 | * BL2/BL2U. |
| 53 | */ |
| 54 | CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_overwrite_bl1); |
| 55 | CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_overwrite_bl1); |
| 56 | |
| 57 | CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2); |
| 58 | CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u); |
| 59 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 60 | static void scp_boot_message_start(void) |
| 61 | { |
| 62 | mhu_secure_message_start(BOM_MHU_SLOT_ID); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 65 | static void scp_boot_message_send(size_t payload_size) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 66 | { |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 67 | /* Ensure that any write to the BOM payload area is seen by SCP before |
| 68 | * we write to the MHU register. If these 2 writes were reordered by |
| 69 | * the CPU then SCP would read stale payload data */ |
| 70 | dmbst(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 71 | |
| 72 | /* Send command to SCP */ |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 73 | mhu_secure_message_send(BOM_MHU_SLOT_ID); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static uint32_t scp_boot_message_wait(size_t size) |
| 77 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 78 | uint32_t mhu_status; |
| 79 | |
| 80 | mhu_status = mhu_secure_message_wait(); |
| 81 | |
| 82 | /* Expect an SCP Boot Protocol message, reject any other protocol */ |
| 83 | if (mhu_status != (1 << BOM_MHU_SLOT_ID)) { |
| 84 | ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", |
| 85 | mhu_status); |
| 86 | panic(); |
| 87 | } |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 88 | |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 89 | /* Ensure that any read to the BOM payload area is done after reading |
| 90 | * the MHU register. If these 2 reads were reordered then the CPU would |
| 91 | * read invalid payload data */ |
| 92 | dmbld(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 93 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 94 | return *(uint32_t *) BOM_SHARED_MEM; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | static void scp_boot_message_end(void) |
| 98 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 99 | mhu_secure_message_end(BOM_MHU_SLOT_ID); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Soby Mathew | 73b7bf9 | 2017-05-03 12:58:41 +0100 | [diff] [blame] | 102 | int css_scp_boot_image_xfer(void *image, unsigned int image_size) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 103 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 104 | uint32_t response; |
| 105 | uint32_t checksum; |
| 106 | cmd_info_payload_t *cmd_info_payload; |
| 107 | cmd_data_payload_t *cmd_data_payload; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 108 | |
Juan Castillo | a72b647 | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 109 | assert((uintptr_t) image == SCP_BL2_BASE); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 110 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 111 | if ((image_size == 0) || (image_size % 4 != 0)) { |
Juan Castillo | a72b647 | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 112 | ERROR("Invalid size for the SCP_BL2 image. Must be a multiple of " |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 113 | "4 bytes and not zero (current size = 0x%x)\n", |
| 114 | image_size); |
| 115 | return -1; |
| 116 | } |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 117 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 118 | /* Extract the checksum from the image */ |
| 119 | checksum = *(uint32_t *) image; |
| 120 | image = (char *) image + sizeof(checksum); |
| 121 | image_size -= sizeof(checksum); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 122 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 123 | mhu_secure_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 124 | |
Juan Castillo | a72b647 | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 125 | VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n"); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 126 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 127 | /* |
| 128 | * Send information about the SCP firmware image about to be transferred |
| 129 | * to SCP |
| 130 | */ |
| 131 | scp_boot_message_start(); |
| 132 | |
| 133 | BOM_CMD_HEADER->id = BOOT_CMD_INFO; |
| 134 | cmd_info_payload = BOM_CMD_PAYLOAD; |
| 135 | cmd_info_payload->image_size = image_size; |
| 136 | cmd_info_payload->checksum = checksum; |
| 137 | |
| 138 | scp_boot_message_send(sizeof(*cmd_info_payload)); |
Sandrine Bailleux | 7da652d | 2015-04-13 11:47:48 +0100 | [diff] [blame] | 139 | #if CSS_DETECT_PRE_1_7_0_SCP |
| 140 | { |
| 141 | const uint32_t deprecated_scp_nack_cmd = 0x404; |
| 142 | uint32_t mhu_status; |
| 143 | |
| 144 | VERBOSE("Detecting SCP version incompatibility\n"); |
| 145 | |
| 146 | mhu_status = mhu_secure_message_wait(); |
| 147 | if (mhu_status == deprecated_scp_nack_cmd) { |
| 148 | ERROR("Detected an incompatible version of the SCP firmware.\n"); |
| 149 | ERROR("Only versions from v1.7.0 onwards are supported.\n"); |
| 150 | ERROR("Please update the SCP firmware.\n"); |
| 151 | return -1; |
| 152 | } |
| 153 | |
| 154 | VERBOSE("SCP version looks OK\n"); |
| 155 | } |
| 156 | #endif /* CSS_DETECT_PRE_1_7_0_SCP */ |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 157 | response = scp_boot_message_wait(sizeof(response)); |
| 158 | scp_boot_message_end(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 159 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 160 | if (response != 0) { |
| 161 | ERROR("SCP BOOT_CMD_INFO returned error %u\n", response); |
| 162 | return -1; |
| 163 | } |
| 164 | |
Juan Castillo | a72b647 | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 165 | VERBOSE("Transferring SCP_BL2 image to SCP\n"); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 166 | |
Juan Castillo | a72b647 | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 167 | /* Transfer SCP_BL2 image to SCP */ |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 168 | scp_boot_message_start(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 169 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 170 | BOM_CMD_HEADER->id = BOOT_CMD_DATA; |
| 171 | cmd_data_payload = BOM_CMD_PAYLOAD; |
Sandrine Bailleux | 47ea1bc | 2015-06-09 11:53:33 +0100 | [diff] [blame] | 172 | cmd_data_payload->offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE; |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 173 | cmd_data_payload->block_size = image_size; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 174 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 175 | scp_boot_message_send(sizeof(*cmd_data_payload)); |
| 176 | response = scp_boot_message_wait(sizeof(response)); |
| 177 | scp_boot_message_end(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 178 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 179 | if (response != 0) { |
| 180 | ERROR("SCP BOOT_CMD_DATA returned error %u\n", response); |
| 181 | return -1; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 182 | } |
| 183 | |
Soby Mathew | 73b7bf9 | 2017-05-03 12:58:41 +0100 | [diff] [blame] | 184 | return 0; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 185 | } |