| Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_F2SDRAMMANAGER_H |
| 8 | #define SOCFPGA_F2SDRAMMANAGER_H |
| 9 | |
| 10 | #include "socfpga_plat_def.h" |
| 11 | |
| 12 | /* FPGA2SDRAM Register Map */ |
| 13 | #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGINSTATUS0 0x14 |
| 14 | #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTCLR0 0x54 |
| 15 | #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTSET0 0x50 |
| 16 | |
| 17 | #define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1)) |
| 18 | #define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4)) |
| 19 | #define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7)) |
| 20 | |
| 21 | #define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0)) |
| 22 | #define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3)) |
| 23 | #define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6)) |
| 24 | #define FLAGINTSTATUS_F2SDRAM0_IDLEACK (BIT(1)) |
| 25 | #define FLAGINTSTATUS_F2SDRAM1_IDLEACK (BIT(5)) |
| 26 | #define FLAGINTSTATUS_F2SDRAM2_IDLEACK (BIT(9)) |
| 27 | #define FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN (BIT(2)) |
| 28 | #define FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN (BIT(5)) |
| 29 | #define FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN (BIT(8)) |
| 30 | |
| 31 | #define FLAGINTSTATUS_F2SOC_RESPEMPTY (BIT(3)) |
| 32 | #define FLAGINTSTATUS_F2SDRAM0_RESPEMPTY (BIT(3)) |
| 33 | #define FLAGINTSTATUS_F2SDRAM1_RESPEMPTY (BIT(7)) |
| 34 | #define FLAGINTSTATUS_F2SDRAM2_RESPEMPTY (BIT(11)) |
| 35 | |
| 36 | #define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \ |
| 37 | + (SOCFPGA_F2SDRAMMGR_##_reg)) |
| 38 | |
| 39 | #endif /* SOCFPGA_F2SDRAMMGR_H */ |