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Masahiro Yamada574388c2016-09-03 11:37:40 +09001/*
Masahiro Yamada75bfecb2017-12-19 11:56:05 +09002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Masahiro Yamada574388c2016-09-03 11:37:40 +09003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Masahiro Yamada574388c2016-09-03 11:37:40 +09009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
11#include <lib/utils_def.h>
12#include <plat/common/common_def.h>
Masahiro Yamada574388c2016-09-03 11:37:40 +090013
14#define PLATFORM_STACK_SIZE 0x1000
15
16#define CACHE_WRITEBACK_SHIFT 6
17#define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT))
18
19/* topology */
20#define UNIPHIER_MAX_CPUS_PER_CLUSTER 4
21#define UNIPHIER_CLUSTER_COUNT 2
22
23#define PLATFORM_CORE_COUNT \
24 ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT))
25
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010026#define PLAT_MAX_PWR_LVL U(1)
Masahiro Yamada574388c2016-09-03 11:37:40 +090027
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010028#define PLAT_MAX_OFF_STATE U(2)
29#define PLAT_MAX_RET_STATE U(1)
Masahiro Yamada574388c2016-09-03 11:37:40 +090030
Masahiro Yamadadb72b0c2018-02-02 15:55:13 +090031#define BL2_BASE ULL(0x80000000)
32#define BL2_LIMIT ULL(0x80080000)
Masahiro Yamadacad2ab52018-01-30 18:49:37 +090033
34/* 0x80080000-0x81000000: reserved for DSP */
35
Masahiro Yamadadb72b0c2018-02-02 15:55:13 +090036#define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL
37#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL
Masahiro Yamada574388c2016-09-03 11:37:40 +090038#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \
39 (UNIPHIER_SEC_DRAM_BASE))
40
Masahiro Yamadadb72b0c2018-02-02 15:55:13 +090041#define BL31_BASE ULL(0x81000000)
42#define BL31_LIMIT ULL(0x81080000)
Masahiro Yamada574388c2016-09-03 11:37:40 +090043
Masahiro Yamadadb72b0c2018-02-02 15:55:13 +090044#define BL32_BASE ULL(0x81080000)
45#define BL32_LIMIT ULL(0x81180000)
Masahiro Yamada574388c2016-09-03 11:37:40 +090046
Masahiro Yamada574388c2016-09-03 11:37:40 +090047#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
48#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
49
50#define PLAT_XLAT_TABLES_DYNAMIC 1
51#define MAX_XLAT_TABLES 7
Masahiro Yamadacad2ab52018-01-30 18:49:37 +090052#define MAX_MMAP_REGIONS 7
Masahiro Yamada574388c2016-09-03 11:37:40 +090053
54#define MAX_IO_HANDLES 2
55#define MAX_IO_DEVICES 2
Yann Gautier37966212018-12-03 13:38:06 +010056#define MAX_IO_BLOCK_DEVICES U(1)
Masahiro Yamada574388c2016-09-03 11:37:40 +090057
Masahiro Yamadad9cf7bb2017-05-15 13:00:00 +090058#define TSP_SEC_MEM_BASE (BL32_BASE)
59#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
Masahiro Yamadad9cf7bb2017-05-15 13:00:00 +090060#define TSP_IRQ_SEC_PHY_TIMER 29
61
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010062#endif /* PLATFORM_DEF_H */