| Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 1 | /* |
| Suyash Pathak | 00b9983 | 2020-02-12 10:36:20 +0530 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
| Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 9 | |
| 10 | #include <sgm_base_platform_def.h> |
| 11 | |
| Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 12 | #define PLAT_MAX_CPUS_PER_CLUSTER U(8) |
| 13 | #define PLAT_MAX_PE_PER_CPU U(1) |
| Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 14 | |
| Suyash Pathak | 00b9983 | 2020-02-12 10:36:20 +0530 | [diff] [blame] | 15 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) |
| 16 | #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) |
| 17 | |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 18 | /* |
| 19 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 20 | */ |
| Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 21 | #ifdef __aarch64__ |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 22 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 23 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 24 | #else |
| 25 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 26 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 27 | #endif |
| 28 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 29 | #endif /* PLATFORM_DEF_H */ |