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git01.mediatek.com / filogic / atf / 72f6fedee0571e1e9c880cfcbd1ae052b17773f8 / . / plat / nvidia / tegra / soc / t186 / plat_smmu.c
blob: b9541e8303937b204d60d78d26c6eee4a198c738 [file] [log] [blame]
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]1/*
Antonio Nino Diaz14ba9632018-03-08 10:57:43 +0000[diff] [blame]2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]3 *
Antonio Nino Diaz14ba9632018-03-08 10:57:43 +0000[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]7#include <common/bl_common.h>
8
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]9#include <smmu.h>
10#include <tegra_def.h>
11
Steven Kao7fd30f52017-07-25 11:29:46 +0800[diff] [blame]12#define MAX_NUM_SMMU_DEVICES U(1)
13
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]14/*******************************************************************************
15 * Array to hold SMMU context for Tegra186
16 ******************************************************************************/
17static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
18 _START_OF_TABLE_,
19 mc_make_sid_security_cfg(SCEW),
20 mc_make_sid_security_cfg(AFIR),
21 mc_make_sid_security_cfg(NVDISPLAYR1),
22 mc_make_sid_security_cfg(XUSB_DEVR),
23 mc_make_sid_security_cfg(VICSRD1),
24 mc_make_sid_security_cfg(NVENCSWR),
25 mc_make_sid_security_cfg(TSECSRDB),
26 mc_make_sid_security_cfg(AXISW),
27 mc_make_sid_security_cfg(SDMMCWAB),
28 mc_make_sid_security_cfg(AONDMAW),
29 mc_make_sid_security_cfg(GPUSWR2),
30 mc_make_sid_security_cfg(SATAW),
31 mc_make_sid_security_cfg(UFSHCW),
32 mc_make_sid_security_cfg(AFIW),
33 mc_make_sid_security_cfg(SDMMCR),
34 mc_make_sid_security_cfg(SCEDMAW),
35 mc_make_sid_security_cfg(UFSHCR),
36 mc_make_sid_security_cfg(SDMMCWAA),
37 mc_make_sid_security_cfg(APEDMAW),
38 mc_make_sid_security_cfg(SESWR),
39 mc_make_sid_security_cfg(MPCORER),
40 mc_make_sid_security_cfg(PTCR),
41 mc_make_sid_security_cfg(BPMPW),
42 mc_make_sid_security_cfg(ETRW),
43 mc_make_sid_security_cfg(GPUSRD),
44 mc_make_sid_security_cfg(VICSWR),
45 mc_make_sid_security_cfg(SCEDMAR),
46 mc_make_sid_security_cfg(HDAW),
47 mc_make_sid_security_cfg(ISPWA),
48 mc_make_sid_security_cfg(EQOSW),
49 mc_make_sid_security_cfg(XUSB_HOSTW),
50 mc_make_sid_security_cfg(TSECSWR),
51 mc_make_sid_security_cfg(SDMMCRAA),
52 mc_make_sid_security_cfg(APER),
53 mc_make_sid_security_cfg(VIW),
54 mc_make_sid_security_cfg(APEW),
55 mc_make_sid_security_cfg(AXISR),
56 mc_make_sid_security_cfg(SDMMCW),
57 mc_make_sid_security_cfg(BPMPDMAW),
58 mc_make_sid_security_cfg(ISPRA),
59 mc_make_sid_security_cfg(NVDECSWR),
60 mc_make_sid_security_cfg(XUSB_DEVW),
61 mc_make_sid_security_cfg(NVDECSRD),
62 mc_make_sid_security_cfg(MPCOREW),
63 mc_make_sid_security_cfg(NVDISPLAYR),
64 mc_make_sid_security_cfg(BPMPDMAR),
65 mc_make_sid_security_cfg(NVJPGSWR),
66 mc_make_sid_security_cfg(NVDECSRD1),
67 mc_make_sid_security_cfg(TSECSRD),
68 mc_make_sid_security_cfg(NVJPGSRD),
69 mc_make_sid_security_cfg(SDMMCWA),
70 mc_make_sid_security_cfg(SCER),
71 mc_make_sid_security_cfg(XUSB_HOSTR),
72 mc_make_sid_security_cfg(VICSRD),
73 mc_make_sid_security_cfg(AONDMAR),
74 mc_make_sid_security_cfg(AONW),
75 mc_make_sid_security_cfg(SDMMCRA),
76 mc_make_sid_security_cfg(HOST1XDMAR),
77 mc_make_sid_security_cfg(EQOSR),
78 mc_make_sid_security_cfg(SATAR),
79 mc_make_sid_security_cfg(BPMPR),
80 mc_make_sid_security_cfg(HDAR),
81 mc_make_sid_security_cfg(SDMMCRAB),
82 mc_make_sid_security_cfg(ETRR),
83 mc_make_sid_security_cfg(AONR),
84 mc_make_sid_security_cfg(APEDMAR),
85 mc_make_sid_security_cfg(SESRD),
86 mc_make_sid_security_cfg(NVENCSRD),
87 mc_make_sid_security_cfg(GPUSWR),
88 mc_make_sid_security_cfg(TSECSWRB),
89 mc_make_sid_security_cfg(ISPWB),
90 mc_make_sid_security_cfg(GPUSRD2),
91 mc_make_sid_override_cfg(APER),
92 mc_make_sid_override_cfg(VICSRD),
93 mc_make_sid_override_cfg(NVENCSRD),
94 mc_make_sid_override_cfg(NVJPGSWR),
95 mc_make_sid_override_cfg(AONW),
96 mc_make_sid_override_cfg(BPMPR),
97 mc_make_sid_override_cfg(BPMPW),
98 mc_make_sid_override_cfg(HDAW),
99 mc_make_sid_override_cfg(NVDISPLAYR1),
100 mc_make_sid_override_cfg(APEDMAR),
101 mc_make_sid_override_cfg(AFIR),
102 mc_make_sid_override_cfg(AXISR),
103 mc_make_sid_override_cfg(VICSRD1),
104 mc_make_sid_override_cfg(TSECSRD),
105 mc_make_sid_override_cfg(BPMPDMAW),
106 mc_make_sid_override_cfg(MPCOREW),
107 mc_make_sid_override_cfg(XUSB_HOSTR),
108 mc_make_sid_override_cfg(GPUSWR),
109 mc_make_sid_override_cfg(XUSB_DEVR),
110 mc_make_sid_override_cfg(UFSHCW),
111 mc_make_sid_override_cfg(XUSB_HOSTW),
112 mc_make_sid_override_cfg(SDMMCWAB),
113 mc_make_sid_override_cfg(SATAW),
114 mc_make_sid_override_cfg(SCEDMAR),
115 mc_make_sid_override_cfg(HOST1XDMAR),
116 mc_make_sid_override_cfg(SDMMCWA),
117 mc_make_sid_override_cfg(APEDMAW),
118 mc_make_sid_override_cfg(SESWR),
119 mc_make_sid_override_cfg(AXISW),
120 mc_make_sid_override_cfg(AONDMAW),
121 mc_make_sid_override_cfg(TSECSWRB),
122 mc_make_sid_override_cfg(MPCORER),
123 mc_make_sid_override_cfg(ISPWB),
124 mc_make_sid_override_cfg(AONR),
125 mc_make_sid_override_cfg(BPMPDMAR),
126 mc_make_sid_override_cfg(HDAR),
127 mc_make_sid_override_cfg(SDMMCRA),
128 mc_make_sid_override_cfg(ETRW),
129 mc_make_sid_override_cfg(GPUSWR2),
130 mc_make_sid_override_cfg(EQOSR),
131 mc_make_sid_override_cfg(TSECSWR),
132 mc_make_sid_override_cfg(ETRR),
133 mc_make_sid_override_cfg(NVDECSRD),
134 mc_make_sid_override_cfg(TSECSRDB),
135 mc_make_sid_override_cfg(SDMMCRAA),
136 mc_make_sid_override_cfg(NVDECSRD1),
137 mc_make_sid_override_cfg(SDMMCR),
138 mc_make_sid_override_cfg(NVJPGSRD),
139 mc_make_sid_override_cfg(SCEDMAW),
140 mc_make_sid_override_cfg(SDMMCWAA),
141 mc_make_sid_override_cfg(APEW),
142 mc_make_sid_override_cfg(AONDMAR),
143 mc_make_sid_override_cfg(PTCR),
144 mc_make_sid_override_cfg(SCER),
145 mc_make_sid_override_cfg(ISPRA),
146 mc_make_sid_override_cfg(ISPWA),
147 mc_make_sid_override_cfg(VICSWR),
148 mc_make_sid_override_cfg(SESRD),
149 mc_make_sid_override_cfg(SDMMCW),
150 mc_make_sid_override_cfg(SDMMCRAB),
151 mc_make_sid_override_cfg(EQOSW),
152 mc_make_sid_override_cfg(GPUSRD2),
153 mc_make_sid_override_cfg(SCEW),
154 mc_make_sid_override_cfg(GPUSRD),
155 mc_make_sid_override_cfg(NVDECSWR),
156 mc_make_sid_override_cfg(XUSB_DEVW),
157 mc_make_sid_override_cfg(SATAR),
158 mc_make_sid_override_cfg(NVDISPLAYR),
159 mc_make_sid_override_cfg(VIW),
160 mc_make_sid_override_cfg(UFSHCR),
161 mc_make_sid_override_cfg(NVENCSWR),
162 mc_make_sid_override_cfg(AFIW),
163 smmu_make_gnsr0_nsec_cfg(CR0),
164 smmu_make_gnsr0_sec_cfg(IDR0),
165 smmu_make_gnsr0_sec_cfg(IDR1),
166 smmu_make_gnsr0_sec_cfg(IDR2),
167 smmu_make_gnsr0_nsec_cfg(GFSR),
168 smmu_make_gnsr0_nsec_cfg(GFSYNR0),
169 smmu_make_gnsr0_nsec_cfg(GFSYNR1),
170 smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
171 smmu_make_gnsr0_nsec_cfg(PIDR2),
172 smmu_make_smrg_group(0),
173 smmu_make_smrg_group(1),
174 smmu_make_smrg_group(2),
175 smmu_make_smrg_group(3),
176 smmu_make_smrg_group(4),
177 smmu_make_smrg_group(5),
178 smmu_make_smrg_group(6),
179 smmu_make_smrg_group(7),
180 smmu_make_smrg_group(8),
181 smmu_make_smrg_group(9),
182 smmu_make_smrg_group(10),
183 smmu_make_smrg_group(11),
184 smmu_make_smrg_group(12),
185 smmu_make_smrg_group(13),
186 smmu_make_smrg_group(14),
187 smmu_make_smrg_group(15),
188 smmu_make_smrg_group(16),
189 smmu_make_smrg_group(17),
190 smmu_make_smrg_group(18),
191 smmu_make_smrg_group(19),
192 smmu_make_smrg_group(20),
193 smmu_make_smrg_group(21),
194 smmu_make_smrg_group(22),
195 smmu_make_smrg_group(23),
196 smmu_make_smrg_group(24),
197 smmu_make_smrg_group(25),
198 smmu_make_smrg_group(26),
199 smmu_make_smrg_group(27),
200 smmu_make_smrg_group(28),
201 smmu_make_smrg_group(29),
202 smmu_make_smrg_group(30),
203 smmu_make_smrg_group(31),
204 smmu_make_smrg_group(32),
205 smmu_make_smrg_group(33),
206 smmu_make_smrg_group(34),
207 smmu_make_smrg_group(35),
208 smmu_make_smrg_group(36),
209 smmu_make_smrg_group(37),
210 smmu_make_smrg_group(38),
211 smmu_make_smrg_group(39),
212 smmu_make_smrg_group(40),
213 smmu_make_smrg_group(41),
214 smmu_make_smrg_group(42),
215 smmu_make_smrg_group(43),
216 smmu_make_smrg_group(44),
217 smmu_make_smrg_group(45),
218 smmu_make_smrg_group(46),
219 smmu_make_smrg_group(47),
220 smmu_make_smrg_group(48),
221 smmu_make_smrg_group(49),
222 smmu_make_smrg_group(50),
223 smmu_make_smrg_group(51),
224 smmu_make_smrg_group(52),
225 smmu_make_smrg_group(53),
226 smmu_make_smrg_group(54),
227 smmu_make_smrg_group(55),
228 smmu_make_smrg_group(56),
229 smmu_make_smrg_group(57),
230 smmu_make_smrg_group(58),
231 smmu_make_smrg_group(59),
232 smmu_make_smrg_group(60),
233 smmu_make_smrg_group(61),
234 smmu_make_smrg_group(62),
235 smmu_make_smrg_group(63),
236 smmu_make_cb_group(0),
237 smmu_make_cb_group(1),
238 smmu_make_cb_group(2),
239 smmu_make_cb_group(3),
240 smmu_make_cb_group(4),
241 smmu_make_cb_group(5),
242 smmu_make_cb_group(6),
243 smmu_make_cb_group(7),
244 smmu_make_cb_group(8),
245 smmu_make_cb_group(9),
246 smmu_make_cb_group(10),
247 smmu_make_cb_group(11),
248 smmu_make_cb_group(12),
249 smmu_make_cb_group(13),
250 smmu_make_cb_group(14),
251 smmu_make_cb_group(15),
252 smmu_make_cb_group(16),
253 smmu_make_cb_group(17),
254 smmu_make_cb_group(18),
255 smmu_make_cb_group(19),
256 smmu_make_cb_group(20),
257 smmu_make_cb_group(21),
258 smmu_make_cb_group(22),
259 smmu_make_cb_group(23),
260 smmu_make_cb_group(24),
261 smmu_make_cb_group(25),
262 smmu_make_cb_group(26),
263 smmu_make_cb_group(27),
264 smmu_make_cb_group(28),
265 smmu_make_cb_group(29),
266 smmu_make_cb_group(30),
267 smmu_make_cb_group(31),
268 smmu_make_cb_group(32),
269 smmu_make_cb_group(33),
270 smmu_make_cb_group(34),
271 smmu_make_cb_group(35),
272 smmu_make_cb_group(36),
273 smmu_make_cb_group(37),
274 smmu_make_cb_group(38),
275 smmu_make_cb_group(39),
276 smmu_make_cb_group(40),
277 smmu_make_cb_group(41),
278 smmu_make_cb_group(42),
279 smmu_make_cb_group(43),
280 smmu_make_cb_group(44),
281 smmu_make_cb_group(45),
282 smmu_make_cb_group(46),
283 smmu_make_cb_group(47),
284 smmu_make_cb_group(48),
285 smmu_make_cb_group(49),
286 smmu_make_cb_group(50),
287 smmu_make_cb_group(51),
288 smmu_make_cb_group(52),
289 smmu_make_cb_group(53),
290 smmu_make_cb_group(54),
291 smmu_make_cb_group(55),
292 smmu_make_cb_group(56),
293 smmu_make_cb_group(57),
294 smmu_make_cb_group(58),
295 smmu_make_cb_group(59),
296 smmu_make_cb_group(60),
297 smmu_make_cb_group(61),
298 smmu_make_cb_group(62),
299 smmu_make_cb_group(63),
300 smmu_bypass_cfg, /* TBU settings */
301 _END_OF_TABLE_,
302};
303
304/*******************************************************************************
305 * Handler to return the pointer to the SMMU's context struct
306 ******************************************************************************/
307smmu_regs_t *plat_get_smmu_ctx(void)
308{
309 /* index of _END_OF_TABLE_ */
Anthony Zhou5a4ce002017-06-28 16:49:16 +0800[diff] [blame]310 tegra186_smmu_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_smmu_context)) - 1U;
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]311
312 return tegra186_smmu_context;
313}
Steven Kao7fd30f52017-07-25 11:29:46 +0800[diff] [blame]314
315/*******************************************************************************
316 * Handler to return the support SMMU devices number
317 ******************************************************************************/
318uint32_t plat_get_num_smmu_devices(void)
319{
320 return MAX_NUM_SMMU_DEVICES;
321}