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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <asm_macros.S>
7#include <platform_def.h>
8
Soby Mathewfec4eb72015-07-01 16:16:20 +01009 .weak plat_arm_calc_core_pos
10 .weak plat_my_core_pos
Dan Handley9df48042015-03-19 18:58:55 +000011 .globl plat_crash_console_init
12 .globl plat_crash_console_putc
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000013 .globl plat_crash_console_flush
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010014 .globl platform_mem_init
dp-armee3457b2017-05-23 09:32:49 +010015 .globl arm_disable_spe
Dan Handley9df48042015-03-19 18:58:55 +000016
Soby Mathewfec4eb72015-07-01 16:16:20 +010017
18 /* -----------------------------------------------------
19 * unsigned int plat_my_core_pos(void)
20 * This function uses the plat_arm_calc_core_pos()
21 * definition to get the index of the calling CPU.
22 * -----------------------------------------------------
23 */
24func plat_my_core_pos
25 mrs x0, mpidr_el1
26 b plat_arm_calc_core_pos
27endfunc plat_my_core_pos
28
29 /* -----------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +010030 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
Soby Mathewfec4eb72015-07-01 16:16:20 +010031 * Helper function to calculate the core position.
32 * With this function: CorePos = (ClusterId * 4) +
33 * CoreId
34 * -----------------------------------------------------
35 */
36func plat_arm_calc_core_pos
37 and x1, x0, #MPIDR_CPU_MASK
38 and x0, x0, #MPIDR_CLUSTER_MASK
39 add x0, x1, x0, LSR #6
40 ret
41endfunc plat_arm_calc_core_pos
Dan Handley9df48042015-03-19 18:58:55 +000042
43 /* ---------------------------------------------
44 * int plat_crash_console_init(void)
45 * Function to initialize the crash console
46 * without a C Runtime to print crash report.
Juan Castilloe7ae6db2015-11-26 14:52:15 +000047 * Clobber list : x0 - x4
Dan Handley9df48042015-03-19 18:58:55 +000048 * ---------------------------------------------
49 */
50func plat_crash_console_init
51 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
52 mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
53 mov_imm x2, ARM_CONSOLE_BAUDRATE
54 b console_core_init
55endfunc plat_crash_console_init
56
57 /* ---------------------------------------------
58 * int plat_crash_console_putc(int c)
59 * Function to print a character on the crash
60 * console without a C Runtime.
61 * Clobber list : x1, x2
62 * ---------------------------------------------
63 */
64func plat_crash_console_putc
65 mov_imm x1, PLAT_ARM_CRASH_UART_BASE
66 b console_core_putc
67endfunc plat_crash_console_putc
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010068
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000069 /* ---------------------------------------------
70 * int plat_crash_console_flush()
71 * Function to force a write of all buffered
72 * data that hasn't been output.
73 * Out : return -1 on error else return 0.
74 * Clobber list : r0 - r1
75 * ---------------------------------------------
76 */
77func plat_crash_console_flush
78 mov_imm x1, PLAT_ARM_CRASH_UART_BASE
79 b console_core_flush
80endfunc plat_crash_console_flush
81
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010082 /* ---------------------------------------------------------------------
83 * We don't need to carry out any memory initialization on ARM
84 * platforms. The Secure RAM is accessible straight away.
85 * ---------------------------------------------------------------------
86 */
87func platform_mem_init
88 ret
89endfunc platform_mem_init
dp-armee3457b2017-05-23 09:32:49 +010090
91 /* -----------------------------------------------------
92 * void arm_disable_spe (void);
93 * -----------------------------------------------------
94 */
95#if ENABLE_SPE_FOR_LOWER_ELS
96func arm_disable_spe
97 /* Detect if SPE is implemented */
98 mrs x0, id_aa64dfr0_el1
99 ubfx x0, x0, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
100 cmp x0, #0x1
101 b.ne 1f
102
103 /* Drain buffered data */
104 .arch armv8.2-a+profile
105 psb csync
106 dsb nsh
107
108 /* Disable Profiling Buffer */
109 mrs x0, pmblimitr_el1
110 bic x0, x0, #1
111 msr pmblimitr_el1, x0
112 isb
113 .arch armv8-a
1141:
115 ret
116endfunc arm_disable_spe
117#endif