Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef MCE_PRIVATE_H |
| 8 | #define MCE_PRIVATE_H |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/mmio.h> |
| 11 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 12 | #include <tegra_def.h> |
| 13 | |
| 14 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 15 | * Macros to prepare CSTATE info request |
| 16 | ******************************************************************************/ |
| 17 | /* Description of the parameters for UPDATE_CSTATE_INFO request */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 18 | #define CLUSTER_CSTATE_MASK ULL(0x7) |
| 19 | #define CLUSTER_CSTATE_SHIFT U(0) |
| 20 | #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7) |
| 21 | #define CCPLEX_CSTATE_MASK ULL(0x3) |
| 22 | #define CCPLEX_CSTATE_SHIFT ULL(8) |
| 23 | #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15) |
| 24 | #define SYSTEM_CSTATE_MASK ULL(0xF) |
| 25 | #define SYSTEM_CSTATE_SHIFT ULL(16) |
| 26 | #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22) |
| 27 | #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22) |
| 28 | #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23) |
| 29 | #define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31) |
| 30 | #define CSTATE_WAKE_MASK_SHIFT ULL(32) |
| 31 | #define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 32 | |
| 33 | /******************************************************************************* |
| 34 | * Auto-CC3 control macros |
| 35 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 36 | #define MCE_AUTO_CC3_FREQ_MASK U(0x1FF) |
| 37 | #define MCE_AUTO_CC3_FREQ_SHIFT U(0) |
| 38 | #define MCE_AUTO_CC3_VTG_MASK U(0x7F) |
| 39 | #define MCE_AUTO_CC3_VTG_SHIFT U(16) |
| 40 | #define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 41 | |
| 42 | /******************************************************************************* |
| 43 | * Macros for the 'IS_SC7_ALLOWED' command |
| 44 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 45 | #define MCE_SC7_ALLOWED_MASK U(0x7) |
| 46 | #define MCE_SC7_WAKE_TIME_SHIFT U(32) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 47 | |
| 48 | /******************************************************************************* |
| 49 | * Macros for 'read/write ctats' commands |
| 50 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 51 | #define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32) |
| 52 | #define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * Macros for 'update crossover threshold' command |
| 56 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 57 | #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 58 | |
| 59 | /******************************************************************************* |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 60 | * MCA argument macros |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 61 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 62 | #define MCA_ARG_ERROR_MASK U(0xFF) |
| 63 | #define MCA_ARG_FINISH_SHIFT U(24) |
| 64 | #define MCA_ARG_FINISH_MASK U(0xFF) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 65 | |
| 66 | /******************************************************************************* |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 67 | * Uncore PERFMON ARI struct |
| 68 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 69 | #define UNCORE_PERFMON_CMD_READ U(0) |
| 70 | #define UNCORE_PERFMON_CMD_WRITE U(1) |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 71 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 72 | #define UNCORE_PERFMON_CMD_MASK U(0xFF) |
| 73 | #define UNCORE_PERFMON_CMD_SHIFT U(24) |
| 74 | #define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF) |
| 75 | #define UNCORE_PERFMON_SELECTOR_MASK U(0xF) |
| 76 | #define UNCORE_PERFMON_REG_MASK U(0xFF) |
| 77 | #define UNCORE_PERFMON_CTR_MASK U(0xFF) |
| 78 | #define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF) |
| 79 | #define UNCORE_PERFMON_RESP_STATUS_SHIFT U(24) |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 80 | |
| 81 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 82 | * Structure populated by arch specific code to export routines which perform |
| 83 | * common low level MCE functions |
| 84 | ******************************************************************************/ |
| 85 | typedef struct arch_mce_ops { |
| 86 | /* |
| 87 | * This ARI request sets up the MCE to start execution on assertion |
| 88 | * of STANDBYWFI, update the core power state and expected wake time, |
| 89 | * then determine the proper power state to enter. |
| 90 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 91 | int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 92 | uint32_t wake_time); |
| 93 | /* |
| 94 | * This ARI request allows updating of the CLUSTER_CSTATE, |
| 95 | * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. |
| 96 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 97 | int32_t (*update_cstate_info)(uint32_t ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 98 | uint32_t cluster, |
| 99 | uint32_t ccplex, |
| 100 | uint32_t system, |
| 101 | uint8_t sys_state_force, |
| 102 | uint32_t wake_mask, |
| 103 | uint8_t update_wake_mask); |
| 104 | /* |
| 105 | * This ARI request allows updating of power state crossover |
| 106 | * threshold times. An index value specifies which crossover |
| 107 | * state is being updated. |
| 108 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 109 | int32_t (*update_crossover_time)(uint32_t ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 110 | uint32_t type, |
| 111 | uint32_t time); |
| 112 | /* |
| 113 | * This ARI request allows read access to statistical information |
| 114 | * related to power states. |
| 115 | */ |
| 116 | uint64_t (*read_cstate_stats)(uint32_t ari_base, |
| 117 | uint32_t state); |
| 118 | /* |
| 119 | * This ARI request allows write access to statistical information |
| 120 | * related to power states. |
| 121 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 122 | int32_t (*write_cstate_stats)(uint32_t ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 123 | uint32_t state, |
| 124 | uint32_t stats); |
| 125 | /* |
| 126 | * This ARI request allows the CPU to understand the features |
| 127 | * supported by the MCE firmware. |
| 128 | */ |
| 129 | uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, |
| 130 | uint32_t data); |
| 131 | /* |
| 132 | * This ARI request allows querying the CCPLEX to determine if |
| 133 | * the CCx state is allowed given a target core C-state and wake |
| 134 | * time. If the CCx state is allowed, the response indicates CCx |
| 135 | * must be entered. If the CCx state is not allowed, the response |
| 136 | * indicates CC6/CC7 can't be entered |
| 137 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 138 | int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 139 | uint32_t wake_time); |
| 140 | /* |
| 141 | * This ARI request allows querying the CCPLEX to determine if |
| 142 | * the SC7 state is allowed given a target core C-state and wake |
| 143 | * time. If the SC7 state is allowed, all cores but the associated |
| 144 | * core are offlined (WAKE_EVENTS are set to 0) and the response |
| 145 | * indicates SC7 must be entered. If the SC7 state is not allowed, |
| 146 | * the response indicates SC7 can't be entered |
| 147 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 148 | int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 149 | uint32_t wake_time); |
| 150 | /* |
| 151 | * This ARI request allows a core to bring another offlined core |
| 152 | * back online to the C0 state. Note that a core is offlined by |
| 153 | * entering a C-state where the WAKE_MASK is all 0. |
| 154 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 155 | int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 156 | /* |
| 157 | * This ARI request allows the CPU to enable/disable Auto-CC3 idle |
| 158 | * state. |
| 159 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 160 | int32_t (*cc3_ctrl)(uint32_t ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 161 | uint32_t freq, |
| 162 | uint32_t volt, |
| 163 | uint8_t enable); |
| 164 | /* |
| 165 | * This ARI request allows updating the reset vector register for |
| 166 | * D15 and A57 CPUs. |
| 167 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 168 | int32_t (*update_reset_vector)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 169 | /* |
| 170 | * This ARI request instructs the ROC to flush A57 data caches in |
| 171 | * order to maintain coherency with the Denver cluster. |
| 172 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 173 | int32_t (*roc_flush_cache)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 174 | /* |
| 175 | * This ARI request instructs the ROC to flush A57 data caches along |
| 176 | * with the caches covering ARM code in order to maintain coherency |
| 177 | * with the Denver cluster. |
| 178 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 179 | int32_t (*roc_flush_cache_trbits)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 180 | /* |
| 181 | * This ARI request instructs the ROC to clean A57 data caches along |
| 182 | * with the caches covering ARM code in order to maintain coherency |
| 183 | * with the Denver cluster. |
| 184 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 185 | int32_t (*roc_clean_cache)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 186 | /* |
| 187 | * This ARI request reads/writes the Machine Check Arch. (MCA) |
| 188 | * registers. |
| 189 | */ |
| 190 | uint64_t (*read_write_mca)(uint32_t ari_base, |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 191 | uint64_t cmd, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 192 | uint64_t *data); |
| 193 | /* |
| 194 | * Some MC GSC (General Security Carveout) register values are |
| 195 | * expected to be changed by TrustZone secure ARM code after boot. |
| 196 | * Since there is no hardware mechanism for the CCPLEX to know |
| 197 | * that an MC GSC register has changed to allow it to update its |
| 198 | * own internal GSC register, there needs to be a mechanism that |
| 199 | * can be used by ARM code to cause the CCPLEX to update its GSC |
| 200 | * register value. This ARI request allows updating the GSC register |
| 201 | * value for a certain carveout in the CCPLEX. |
| 202 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 203 | int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 204 | /* |
| 205 | * This ARI request instructs the CCPLEX to either shutdown or |
| 206 | * reset the entire system |
| 207 | */ |
| 208 | void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 209 | /* |
| 210 | * This ARI request reads/writes data from/to Uncore PERFMON |
| 211 | * registers |
| 212 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 213 | int32_t (*read_write_uncore_perfmon)(uint32_t ari_base, |
| 214 | uint64_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 215 | /* |
| 216 | * This ARI implements ARI_MISC_CCPLEX commands. This can be |
| 217 | * used to enable/disable coresight clock gating. |
| 218 | */ |
| 219 | void (*misc_ccplex)(uint32_t ari_base, uint32_t index, |
| 220 | uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 221 | } arch_mce_ops_t; |
| 222 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 223 | /* declarations for ARI/NVG handler functions */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 224 | int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 225 | int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 226 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 227 | uint8_t update_wake_mask); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 228 | int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 229 | uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 230 | int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 231 | uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 232 | int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 233 | int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 234 | int32_t ari_online_core(uint32_t ari_base, uint32_t core); |
| 235 | int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
| 236 | int32_t ari_reset_vector_update(uint32_t ari_base); |
| 237 | int32_t ari_roc_flush_cache_trbits(uint32_t ari_base); |
| 238 | int32_t ari_roc_flush_cache(uint32_t ari_base); |
| 239 | int32_t ari_roc_clean_cache(uint32_t ari_base); |
| 240 | uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data); |
| 241 | int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 242 | void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 243 | int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, |
| 244 | uint64_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 245 | void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 246 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 247 | int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 248 | int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 249 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 250 | uint8_t update_wake_mask); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 251 | int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 252 | uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 253 | int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); |
| 254 | int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 255 | int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 256 | int32_t nvg_online_core(uint32_t ari_base, uint32_t core); |
| 257 | int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 258 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 259 | extern void nvg_set_request_data(uint64_t req, uint64_t data); |
| 260 | extern void nvg_set_request(uint64_t req); |
| 261 | extern uint64_t nvg_get_result(void); |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 262 | #endif /* MCE_PRIVATE_H */ |