blob: c074e85d14860f3d485234f6eca0fe5c99454d35 [file] [log] [blame]
Haojian Zhuang20cd3232017-05-31 11:00:15 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef UFS_H
8#define UFS_H
Haojian Zhuang20cd3232017-05-31 11:00:15 +08009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
fengbaopeng44070ef2018-02-12 20:53:54 +080011
Haojian Zhuang20cd3232017-05-31 11:00:15 +080012/* register map of UFSHCI */
13/* Controller Capabilities */
14#define CAP 0x00
15#define CAP_NUTRS_MASK 0x1F
16
17/* UFS Version */
18#define VER 0x08
19/* Host Controller Identification - Product ID */
20#define HCDDID 0x10
21/* Host Controller Identification Descriptor - Manufacturer ID */
22#define HCPMID 0x14
23/* Auto-Hibernate Idle Timer */
24#define AHIT 0x18
25/* Interrupt Status */
26#define IS 0x20
27/* Interrupt Enable */
28#define IE 0x24
29/* System Bus Fatal Error Status */
30#define UFS_INT_SBFES (1 << 17)
31/* Host Controller Fatal Error Status */
32#define UFS_INT_HCFES (1 << 16)
33/* UTP Error Status */
34#define UFS_INT_UTPES (1 << 12)
35/* Device Fatal Error Status */
36#define UFS_INT_DFES (1 << 11)
37/* UIC Command Completion Status */
38#define UFS_INT_UCCS (1 << 10)
39/* UTP Task Management Request Completion Status */
40#define UFS_INT_UTMRCS (1 << 9)
41/* UIC Link Startup Status */
42#define UFS_INT_ULSS (1 << 8)
43/* UIC Link Lost Status */
44#define UFS_INT_ULLS (1 << 7)
45/* UIC Hibernate Enter Status */
46#define UFS_INT_UHES (1 << 6)
47/* UIC Hibernate Exit Status */
48#define UFS_INT_UHXS (1 << 5)
49/* UIC Power Mode Status */
50#define UFS_INT_UPMS (1 << 4)
51/* UIC Test Mode Status */
52#define UFS_INT_UTMS (1 << 3)
53/* UIC Error */
54#define UFS_INT_UE (1 << 2)
55/* UIC DME_ENDPOINTRESET Indication */
56#define UFS_INT_UDEPRI (1 << 1)
57/* UTP Transfer Request Completion Status */
58#define UFS_INT_UTRCS (1 << 0)
59
60/* Host Controller Status */
61#define HCS 0x30
62#define HCS_UPMCRS_MASK (7 << 8)
63#define HCS_PWR_LOCAL (1 << 8)
64#define HCS_UCRDY (1 << 3)
65#define HCS_UTMRLRDY (1 << 2)
66#define HCS_UTRLRDY (1 << 1)
67#define HCS_DP (1 << 0)
68
69/* Host Controller Enable */
70#define HCE 0x34
71#define HCE_ENABLE 1
72
73/* Host UIC Error Code PHY Adapter Layer */
74#define UECPA 0x38
75/* Host UIC Error Code Data Link Layer */
76#define UECDL 0x3C
77/* Host UIC Error Code Network Layer */
78#define UECN 0x40
79/* Host UIC Error Code Transport Layer */
80#define UECT 0x44
81/* Host UIC Error Code */
82#define UECDME 0x48
83/* UTP Transfer Request Interrupt Aggregation Control Register */
84#define UTRIACR 0x4C
Justin Chadwell82946022019-07-03 14:15:22 +010085#define UTRIACR_IAEN (1U << 31)
Haojian Zhuang20cd3232017-05-31 11:00:15 +080086#define UTRIACR_IAPWEN (1 << 24)
87#define UTRIACR_IASB (1 << 20)
88#define UTRIACR_CTR (1 << 16)
89#define UTRIACR_IACTH(x) (((x) & 0x1F) << 8)
90#define UTRIACR_IATOVAL(x) ((x) & 0xFF)
91
92/* UTP Transfer Request List Base Address */
93#define UTRLBA 0x50
94/* UTP Transfer Request List Base Address Upper 32-bits */
95#define UTRLBAU 0x54
96/* UTP Transfer Request List Door Bell Register */
97#define UTRLDBR 0x58
98/* UTP Transfer Request List Clear Register */
99#define UTRLCLR 0x5C
100/* UTP Transfer Request List Run Stop Register */
101#define UTRLRSR 0x60
102#define UTMRLBA 0x70
103#define UTMRLBAU 0x74
104#define UTMRLDBR 0x78
105#define UTMRLCLR 0x7C
106#define UTMRLRSR 0x80
107/* UIC Command */
108#define UICCMD 0x90
109/* UIC Command Argument 1 */
110#define UCMDARG1 0x94
111/* UIC Command Argument 2 */
112#define UCMDARG2 0x98
113/* UIC Command Argument 3 */
114#define UCMDARG3 0x9C
115
116#define UFS_BLOCK_SHIFT 12 /* 4KB */
117#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT)
118#define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1)
119#define UFS_MAX_LUNS 8
120
121/* UTP Transfer Request Descriptor */
122/* Command Type */
123#define CT_UFS_STORAGE 1
124#define CT_SCSI 0
125
126/* Data Direction */
127#define DD_OUT 2 /* Device --> Host */
128#define DD_IN 1 /* Host --> Device */
129#define DD_NO_DATA_TRANSFER 0
130
131#define UTP_TRD_SIZE 32
132
133/* Transaction Type */
134#define TRANS_TYPE_HD (1 << 7) /* E2ECRC */
135#define TRANS_TYPE_DD (1 << 6)
136#define TRANS_TYPE_CODE_MASK 0x3F
137#define QUERY_RESPONSE_UPIU (0x36 << 0)
138#define READY_TO_TRANSACTION_UPIU (0x31 << 0)
139#define DATA_IN_UPIU (0x22 << 0)
140#define RESPONSE_UPIU (0x21 << 0)
141#define NOP_IN_UPIU (0x20 << 0)
142#define QUERY_REQUEST_UPIU (0x16 << 0)
143#define DATA_OUT_UPIU (0x02 << 0)
144#define CMD_UPIU (0x01 << 0)
145#define NOP_OUT_UPIU (0x00 << 0)
146
147#define OCS_SUCCESS 0x0
148#define OCS_INVALID_FUNC_ATTRIBUTE 0x1
149#define OCS_MISMATCH_REQUEST_SIZE 0x2
150#define OCS_MISMATCH_RESPONSE_SIZE 0x3
151#define OCS_PEER_COMMUNICATION_FAILURE 0x4
152#define OCS_ABORTED 0x5
153#define OCS_FATAL_ERROR 0x6
154#define OCS_MASK 0xF
155
156/* UIC Command */
157#define DME_GET 0x01
158#define DME_SET 0x02
159#define DME_PEER_GET 0x03
160#define DME_PEER_SET 0x04
161#define DME_POWERON 0x10
162#define DME_POWEROFF 0x11
163#define DME_ENABLE 0x12
164#define DME_RESET 0x14
165#define DME_ENDPOINTRESET 0x15
166#define DME_LINKSTARTUP 0x16
167#define DME_HIBERNATE_ENTER 0x17
168#define DME_HIBERNATE_EXIT 0x18
169#define DME_TEST_MODE 0x1A
170
171#define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF)
172
173#define CONFIG_RESULT_CODE_MASK 0xFF
174
175#define CDBCMD_TEST_UNIT_READY 0x00
176#define CDBCMD_READ_6 0x08
177#define CDBCMD_WRITE_6 0x0A
178#define CDBCMD_START_STOP_UNIT 0x1B
179#define CDBCMD_READ_CAPACITY_10 0x25
180#define CDBCMD_READ_10 0x28
181#define CDBCMD_WRITE_10 0x2A
182#define CDBCMD_READ_16 0x88
183#define CDBCMD_WRITE_16 0x8A
184#define CDBCMD_READ_CAPACITY_16 0x9E
185#define CDBCMD_REPORT_LUNS 0xA0
186
187#define UPIU_FLAGS_R (1 << 6)
188#define UPIU_FLAGS_W (1 << 5)
189#define UPIU_FLAGS_ATTR_MASK (3 << 0)
190#define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */
191#define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */
192#define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */
193#define UPIU_FLAGS_ATTR_ACA (3 << 0)
194#define UPIU_FLAGS_O (1 << 6)
195#define UPIU_FLAGS_U (1 << 5)
196#define UPIU_FLAGS_D (1 << 4)
197
198#define QUERY_FUNC_STD_READ 0x01
199#define QUERY_FUNC_STD_WRITE 0x81
200
201#define QUERY_NOP 0x00
202#define QUERY_READ_DESC 0x01
203#define QUERY_WRITE_DESC 0x02
204#define QUERY_READ_ATTR 0x03
205#define QUERY_WRITE_ATTR 0x04
206#define QUERY_READ_FLAG 0x05
207#define QUERY_SET_FLAG 0x06
208#define QUERY_CLEAR_FLAG 0x07
209#define QUERY_TOGGLE_FLAG 0x08
210
211#define RW_WITHOUT_CACHE 0x18
212
213#define DESC_TYPE_DEVICE 0x00
214#define DESC_TYPE_CONFIGURATION 0x01
215#define DESC_TYPE_UNIT 0x02
216#define DESC_TYPE_INTERCONNECT 0x04
217#define DESC_TYPE_STRING 0x05
218
fengbaopeng44070ef2018-02-12 20:53:54 +0800219#define DESC_DEVICE_MAX_SIZE 0x1F
220#define DEVICE_DESC_PARAM_MANF_ID 0x18
221
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800222#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
223#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
224
225#define DEVICE_DESCRIPTOR_LEN 0x40
226#define UNIT_DESCRIPTOR_LEN 0x23
227
228#define QUERY_RESP_SUCCESS 0x00
229#define QUERY_RESP_OPCODE 0xFE
230#define QUERY_RESP_GENERAL_FAIL 0xFF
231
232#define SENSE_KEY_NO_SENSE 0x00
233#define SENSE_KEY_RECOVERED_ERROR 0x01
234#define SENSE_KEY_NOT_READY 0x02
235#define SENSE_KEY_MEDIUM_ERROR 0x03
236#define SENSE_KEY_HARDWARE_ERROR 0x04
237#define SENSE_KEY_ILLEGAL_REQUEST 0x05
238#define SENSE_KEY_UNIT_ATTENTION 0x06
239#define SENSE_KEY_DATA_PROTECT 0x07
240#define SENSE_KEY_BLANK_CHECK 0x08
241#define SENSE_KEY_VENDOR_SPECIFIC 0x09
242#define SENSE_KEY_COPY_ABORTED 0x0A
243#define SENSE_KEY_ABORTED_COMMAND 0x0B
244#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
245#define SENSE_KEY_MISCOMPARE 0x0E
246
247#define SENSE_DATA_VALID 0x70
248#define SENSE_DATA_LENGTH 18
249
250#define READ_CAPACITY_LENGTH 8
251
252#define FLAG_DEVICE_INIT 0x01
253
fengbaopeng44070ef2018-02-12 20:53:54 +0800254#define UFS_VENDOR_SKHYNIX U(0x1AD)
255
256#define MAX_MODEL_LEN 16
Jorge Troncoso453e5e72021-09-23 17:14:29 -0700257
258/* maximum number of retries for a general UIC command */
259#define UFS_UIC_COMMAND_RETRIES 3
260
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700261/* maximum number of link-startup retries */
262#define DME_LINKSTARTUP_RETRIES 10
263
Jorge Troncoso5f449162021-09-30 16:29:32 -0700264#define HCE_ENABLE_OUTER_RETRIES 3
265#define HCE_ENABLE_INNER_RETRIES 50
266#define HCE_ENABLE_TIMEOUT_US 100
267
fengbaopeng44070ef2018-02-12 20:53:54 +0800268/**
269 * ufs_dev_desc - ufs device details from the device descriptor
270 * @wmanufacturerid: card details
271 * @model: card model
272 */
273struct ufs_dev_desc {
274 uint16_t wmanufacturerid;
275 int8_t model[MAX_MODEL_LEN + 1];
276};
277
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800278/* UFS Driver Flags */
279#define UFS_FLAGS_SKIPINIT (1 << 0)
fengbaopeng44070ef2018-02-12 20:53:54 +0800280#define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2)
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800281
282typedef struct sense_data {
283 uint8_t resp_code : 7;
284 uint8_t valid : 1;
285 uint8_t reserved0;
286 uint8_t sense_key : 4;
287 uint8_t reserved1 : 1;
288 uint8_t ili : 1;
289 uint8_t eom : 1;
290 uint8_t file_mark : 1;
291 uint8_t info[4];
292 uint8_t asl;
293 uint8_t cmd_spec_len[4];
294 uint8_t asc;
295 uint8_t ascq;
296 uint8_t fruc;
297 uint8_t sense_key_spec0 : 7;
298 uint8_t sksv : 1;
299 uint8_t sense_key_spec1;
300 uint8_t sense_key_spec2;
301} sense_data_t;
302
303/* UTP Transfer Request Descriptor */
304typedef struct utrd_header {
305 uint32_t reserved0 : 24;
306 uint32_t i : 1; /* interrupt */
307 uint32_t dd : 2; /* data direction */
308 uint32_t reserved1 : 1;
309 uint32_t ct : 4; /* command type */
310 uint32_t reserved2;
311 uint32_t ocs : 8; /* Overall Command Status */
312 uint32_t reserved3 : 24;
313 uint32_t reserved4;
314 uint32_t ucdba; /* aligned to 128-byte */
315 uint32_t ucdbau; /* Upper 32-bits */
316 uint32_t rul : 16; /* Response UPIU Length */
317 uint32_t ruo : 16; /* Response UPIU Offset */
318 uint32_t prdtl : 16; /* PRDT Length */
319 uint32_t prdto : 16; /* PRDT Offset */
320} utrd_header_t; /* 8 words with little endian */
321
322/* UTP Task Management Request Descriptor */
323typedef struct utp_utmrd {
324 /* 4 words with little endian */
325 uint32_t reserved0 : 24;
326 uint32_t i : 1; /* interrupt */
327 uint32_t reserved1 : 7;
328 uint32_t reserved2;
329 uint32_t ocs : 8; /* Overall Command Status */
330 uint32_t reserved3 : 24;
331 uint32_t reserved4;
332
333 /* followed by 8 words UPIU with big endian */
334
335 /* followed by 8 words Response UPIU with big endian */
336} utp_utmrd_t;
337
338/* NOP OUT UPIU */
339typedef struct nop_out_upiu {
340 uint8_t trans_type;
341 uint8_t flags;
342 uint8_t reserved0;
343 uint8_t task_tag;
344 uint8_t reserved1;
345 uint8_t reserved2;
346 uint8_t reserved3;
347 uint8_t reserved4;
348 uint8_t total_ehs_len;
349 uint8_t reserved5;
350 uint16_t data_segment_len;
351 uint32_t reserved6;
352 uint32_t reserved7;
353 uint32_t reserved8;
354 uint32_t reserved9;
355 uint32_t reserved10;
356 uint32_t e2ecrc;
357} nop_out_upiu_t; /* 36 bytes with big endian */
358
359/* NOP IN UPIU */
360typedef struct nop_in_upiu {
361 uint8_t trans_type;
362 uint8_t flags;
363 uint8_t reserved0;
364 uint8_t task_tag;
365 uint8_t reserved1;
366 uint8_t reserved2;
367 uint8_t response;
368 uint8_t reserved3;
369 uint8_t total_ehs_len;
370 uint8_t dev_info;
371 uint16_t data_segment_len;
372 uint32_t reserved4;
373 uint32_t reserved5;
374 uint32_t reserved6;
375 uint32_t reserved7;
376 uint32_t reserved8;
377 uint32_t e2ecrc;
378} nop_in_upiu_t; /* 36 bytes with big endian */
379
380/* Command UPIU */
381typedef struct cmd_upiu {
382 uint8_t trans_type;
383 uint8_t flags;
384 uint8_t lun;
385 uint8_t task_tag;
386 uint8_t cmd_set_type;
387 uint8_t reserved0;
388 uint8_t reserved1;
389 uint8_t reserved2;
390 uint8_t total_ehs_len;
391 uint8_t reserved3;
392 uint16_t data_segment_len;
393 uint32_t exp_data_trans_len;
394 /*
395 * A CDB has a fixed length of 16bytes or a variable length
396 * of between 12 and 260 bytes
397 */
398 uint8_t cdb[16]; /* little endian */
399} cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */
400
401typedef struct query_desc {
402 uint8_t opcode;
403 uint8_t idn;
404 uint8_t index;
405 uint8_t selector;
406 uint8_t reserved0[2];
407 uint16_t length;
408 uint32_t reserved2[2];
409} query_desc_t; /* 16 bytes with big endian */
410
411typedef struct query_flag {
412 uint8_t opcode;
413 uint8_t idn;
414 uint8_t index;
415 uint8_t selector;
416 uint8_t reserved0[7];
417 uint8_t value;
418 uint32_t reserved8;
419} query_flag_t; /* 16 bytes with big endian */
420
421typedef struct query_attr {
422 uint8_t opcode;
423 uint8_t idn;
424 uint8_t index;
425 uint8_t selector;
426 uint8_t reserved0[4];
427 uint32_t value; /* little endian */
428 uint32_t reserved4;
429} query_attr_t; /* 16 bytes with big endian except for value */
430
431/* Query Request UPIU */
432typedef struct query_upiu {
433 uint8_t trans_type;
434 uint8_t flags;
435 uint8_t reserved0;
436 uint8_t task_tag;
437 uint8_t reserved1;
438 uint8_t query_func;
439 uint8_t reserved2;
440 uint8_t reserved3;
441 uint8_t total_ehs_len;
442 uint8_t reserved4;
443 uint16_t data_segment_len;
444 /* Transaction Specific Fields */
445 union {
446 query_desc_t desc;
447 query_flag_t flag;
448 query_attr_t attr;
449 } ts;
450 uint32_t reserved5;
451} query_upiu_t; /* 32 bytes with big endian */
452
453/* Query Response UPIU */
454typedef struct query_resp_upiu {
455 uint8_t trans_type;
456 uint8_t flags;
457 uint8_t reserved0;
458 uint8_t task_tag;
459 uint8_t reserved1;
460 uint8_t query_func;
461 uint8_t query_resp;
462 uint8_t reserved2;
463 uint8_t total_ehs_len;
464 uint8_t dev_info;
465 uint16_t data_segment_len;
466 union {
467 query_desc_t desc;
468 query_flag_t flag;
469 query_attr_t attr;
470 } ts;
471 uint32_t reserved3;
472} query_resp_upiu_t; /* 32 bytes with big endian */
473
474/* Response UPIU */
475typedef struct resp_upiu {
476 uint8_t trans_type;
477 uint8_t flags;
478 uint8_t lun;
479 uint8_t task_tag;
480 uint8_t cmd_set_type;
481 uint8_t reserved0;
482 uint8_t reserved1;
483 uint8_t status;
484 uint8_t total_ehs_len;
485 uint8_t dev_info;
486 uint16_t data_segment_len;
487 uint32_t res_trans_cnt; /* Residual Transfer Count */
488 uint32_t reserved2[4];
489 uint16_t sense_data_len;
490 union {
491 uint8_t sense_data[18];
492 sense_data_t sense;
493 } sd;
494} resp_upiu_t; /* 52 bytes with big endian */
495
496typedef struct cmd_info {
497 uintptr_t buf;
498 size_t length;
499 int lba;
500 uint8_t op;
501 uint8_t direction;
502 uint8_t lun;
503} cmd_info_t;
504
505typedef struct utp_utrd {
506 uintptr_t header; /* utrd_header_t */
507 uintptr_t upiu;
508 uintptr_t resp_upiu;
509 uintptr_t prdt;
510 size_t size_upiu;
511 size_t size_resp_upiu;
512 size_t size_prdt;
513 int task_tag;
514} utp_utrd_t;
515
516/* Physical Region Description Table */
517typedef struct prdt {
518 uint32_t dba; /* Data Base Address */
519 uint32_t dbau; /* Data Base Address Upper 32-bits */
520 uint32_t reserved0;
521 uint32_t dbc : 18; /* Data Byte Count */
522 uint32_t reserved1 : 14;
523} prdt_t;
524
525typedef struct uic_cmd {
526 uint32_t op;
527 uint32_t arg1;
528 uint32_t arg2;
529 uint32_t arg3;
530} uic_cmd_t;
531
532typedef struct ufs_params {
533 uintptr_t reg_base;
534 uintptr_t desc_base;
535 size_t desc_size;
536 unsigned long flags;
537} ufs_params_t;
538
539typedef struct ufs_ops {
540 int (*phy_init)(ufs_params_t *params);
541 int (*phy_set_pwr_mode)(ufs_params_t *params);
542} ufs_ops_t;
543
544int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd);
545int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val);
546int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val);
547
548unsigned int ufs_read_attr(int idn);
549void ufs_write_attr(int idn, unsigned int value);
550unsigned int ufs_read_flag(int idn);
551void ufs_set_flag(int idn);
552void ufs_clear_flag(int idn);
553void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size);
554void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size);
555size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size);
556size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size);
557int ufs_init(const ufs_ops_t *ops, ufs_params_t *params);
558
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000559#endif /* UFS_H */