| Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <gicv2.h> |
| 8 | #include <debug.h> |
| 9 | #include "ls_16550.h" |
| 10 | #include "plat_ls.h" |
| 11 | #include "soc.h" |
| 12 | |
| 13 | #define BL32_END (unsigned long)(&__BL32_END__) |
| 14 | |
| 15 | const unsigned int g0_interrupt_array1[] = { |
| 16 | 9 |
| 17 | }; |
| 18 | |
| 19 | gicv2_driver_data_t ls_gic_data = { |
| 20 | .gicd_base = GICD_BASE, |
| 21 | .gicc_base = GICC_BASE, |
| 22 | .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array1), |
| 23 | .g0_interrupt_array = g0_interrupt_array1, |
| 24 | }; |
| 25 | |
| 26 | /******************************************************************************* |
| 27 | * Initialize the UART |
| 28 | ******************************************************************************/ |
| 29 | void ls_tsp_early_platform_setup(void) |
| 30 | { |
| 31 | static console_ls_16550_t console; |
| 32 | /* |
| 33 | * Initialize a different console than already in use to display |
| 34 | * messages from TSP |
| 35 | */ |
| 36 | console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK, |
| 37 | PLAT_LS1043_UART_BAUDRATE, &console); |
| 38 | NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32); |
| 39 | } |
| 40 | |
| 41 | /******************************************************************************* |
| 42 | * Perform platform specific setup placeholder |
| 43 | ******************************************************************************/ |
| 44 | void tsp_platform_setup(void) |
| 45 | { |
| 46 | uint32_t gicc_base, gicd_base; |
| 47 | |
| 48 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 49 | get_gic_offset(&gicc_base, &gicd_base); |
| 50 | ls_gic_data.gicd_base = (uintptr_t)gicd_base; |
| 51 | ls_gic_data.gicc_base = (uintptr_t)gicc_base; |
| 52 | gicv2_driver_init(&ls_gic_data); |
| 53 | gicv2_distif_init(); |
| 54 | gicv2_pcpu_distif_init(); |
| 55 | gicv2_cpuif_enable(); |
| 56 | } |
| 57 | |
| 58 | /******************************************************************************* |
| 59 | * Perform the very early platform specific architectural setup here. At the |
| 60 | * moment this is only intializes the MMU |
| 61 | ******************************************************************************/ |
| 62 | void tsp_plat_arch_setup(void) |
| 63 | { |
| 64 | ls_setup_page_tables(BL32_BASE, |
| 65 | (BL32_END - BL32_BASE), |
| 66 | BL_CODE_BASE, |
| 67 | BL_CODE_END, |
| 68 | BL_RO_DATA_BASE, |
| 69 | BL_RO_DATA_END |
| 70 | #if USE_COHERENT_MEM |
| 71 | , BL_COHERENT_RAM_BASE, |
| 72 | BL_COHERENT_RAM_END |
| 73 | #endif |
| 74 | ); |
| 75 | enable_mmu_el1(0); |
| 76 | } |