Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 1 | /* |
Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 2 | * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. |
Jit Loon Lim | 28c1c78 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 3 | * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_SOCFPGA_DEF_H |
| 9 | #define PLAT_SOCFPGA_DEF_H |
| 10 | |
Jit Loon Lim | 28c1c78 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 11 | #include "n5x_system_manager.h" |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 12 | #include <platform_def.h> |
| 13 | |
| 14 | /* Platform Setting */ |
Jit Loon Lim | 28c1c78 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 15 | #define PLATFORM_MODEL PLAT_SOCFPGA_N5X |
| 16 | #define BOOT_SOURCE BOOT_SOURCE_SDMMC |
| 17 | #define PLAT_PRIMARY_CPU 0 |
| 18 | #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT |
| 19 | #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 20 | |
Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 21 | /* FPGA config helpers */ |
| 22 | #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 |
| 23 | #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 |
| 24 | |
Jit Loon Lim | 28c1c78 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 25 | /* QSPI Setting */ |
| 26 | #define CAD_QSPIDATA_OFST 0xff900000 |
| 27 | #define CAD_QSPI_OFFSET 0xff8d2000 |
| 28 | |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 29 | /* Register Mapping */ |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 30 | #define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000) |
| 31 | #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) |
| 32 | |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 33 | #define SOCFPGA_MMC_REG_BASE U(0xff808000) |
| 34 | |
| 35 | #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) |
| 36 | #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) |
| 37 | |
| 38 | #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) |
| 39 | #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) |
| 40 | #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) |
| 41 | #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) |
| 42 | |
Jit Loon Lim | 28c1c78 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 43 | |
| 44 | /******************************************************************************* |
| 45 | * Platform memory map related constants |
| 46 | ******************************************************************************/ |
| 47 | #define DRAM_BASE (0x0) |
| 48 | #define DRAM_SIZE (0x80000000) |
| 49 | |
| 50 | #define OCRAM_BASE (0xFFE00000) |
| 51 | #define OCRAM_SIZE (0x00040000) |
| 52 | |
| 53 | #define MEM64_BASE (0x0100000000) |
| 54 | #define MEM64_SIZE (0x1F00000000) |
| 55 | |
| 56 | #define DEVICE1_BASE (0x80000000) |
| 57 | #define DEVICE1_SIZE (0x60000000) |
| 58 | |
| 59 | #define DEVICE2_BASE (0xF7000000) |
| 60 | #define DEVICE2_SIZE (0x08E00000) |
| 61 | |
| 62 | #define DEVICE3_BASE (0xFFFC0000) |
| 63 | #define DEVICE3_SIZE (0x00008000) |
| 64 | |
| 65 | #define DEVICE4_BASE (0x2000000000) |
| 66 | #define DEVICE4_SIZE (0x0100000000) |
| 67 | |
| 68 | #define BL2_BASE (0xffe00000) |
| 69 | #define BL2_LIMIT (0xffe1b000) |
| 70 | |
| 71 | #define BL31_BASE (0x1000) |
| 72 | #define BL31_LIMIT (0x81000) |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * UART related constants |
| 76 | ******************************************************************************/ |
| 77 | #define PLAT_UART0_BASE (0xFFC02000) |
| 78 | #define PLAT_UART1_BASE (0xFFC02100) |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * GIC related constants |
| 82 | ******************************************************************************/ |
| 83 | #define PLAT_GIC_BASE (0xFFFC0000) |
| 84 | #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) |
| 85 | #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) |
| 86 | #define PLAT_GICR_BASE 0 |
| 87 | |
| 88 | #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) |
| 89 | #define PLAT_HZ_CONVERT_TO_MHZ (1000000) |
| 90 | |
| 91 | /* Platform specific system counter */ |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 92 | #define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk() |
BenjaminLimJL | a4a4327 | 2022-04-06 10:19:16 +0800 | [diff] [blame] | 93 | |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 94 | #endif /* PLAT_SOCFPGA_DEF_H */ |