blob: 8bee4fef8909f2f313595e68c8433f6a63f5712f [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_def.h>
32#include <debug.h>
33#include <platform_def.h>
34#include <tzc400.h>
35
36
37/* Weak definitions may be overridden in specific ARM standard platform */
38#pragma weak plat_arm_security_setup
39
40
41/*******************************************************************************
42 * Initialize the TrustZone Controller for ARM standard platforms.
43 * Configure Region 0 with no access, Region 1 with secure access only, and
44 * the remaining DRAM regions access from the given Non-Secure masters.
45 ******************************************************************************/
46void arm_tzc_setup(void)
47{
48 INFO("Configuring TrustZone Controller\n");
49
50 tzc_init(ARM_TZC_BASE);
51
52 /* Disable filters. */
53 tzc_disable_filters();
54
55 /* Region 0 set to no access by default */
56 tzc_configure_region0(TZC_REGION_S_NONE, 0);
57
58 /* Region 1 set to cover Secure part of DRAM */
59 tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1,
60 ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
61 TZC_REGION_S_RDWR,
62 0);
63
64 /* Region 2 set to cover Non-Secure access to 1st DRAM address range.
65 * Apply the same configuration to given filters in the TZC. */
66 tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2,
67 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
68 TZC_REGION_S_NONE,
69 PLAT_ARM_TZC_NS_DEV_ACCESS);
70
71 /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
72 tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3,
73 ARM_DRAM2_BASE, ARM_DRAM2_END,
74 TZC_REGION_S_NONE,
75 PLAT_ARM_TZC_NS_DEV_ACCESS);
76
77 /*
78 * Raise an exception if a NS device tries to access secure memory
79 * TODO: Add interrupt handling support.
80 */
81 tzc_set_action(TZC_ACTION_ERR);
82
83 /* Enable filters. */
84 tzc_enable_filters();
85}
86
87void plat_arm_security_setup(void)
88{
89 arm_tzc_setup();
90}