Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 32 | #include <platform.h> |
| 33 | #include <tzc400.h> |
| 34 | #include <debug.h> |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 35 | |
| 36 | /* Used to improve readability for configuring regions. */ |
| 37 | #define FILTER_SHIFT(filter) (1 << filter) |
| 38 | |
| 39 | /* |
| 40 | * For the moment we assume that all security programming is done by the |
| 41 | * primary core. |
| 42 | * TODO: |
| 43 | * Might want to enable interrupt on violations when supported? |
| 44 | */ |
| 45 | void plat_security_setup(void) |
| 46 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 47 | tzc_instance_t controller; |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * The Base FVP has a TrustZone address space controller, the Foundation |
| 51 | * FVP does not. Trying to program the device on the foundation FVP will |
| 52 | * cause an abort. |
| 53 | * |
| 54 | * If the platform had additional peripheral specific security |
| 55 | * configurations, those would be configured here. |
| 56 | */ |
| 57 | |
| 58 | if (!platform_get_cfgvar(CONFIG_HAS_TZC)) |
| 59 | return; |
| 60 | |
| 61 | /* |
| 62 | * The TrustZone controller controls access to main DRAM. Give |
| 63 | * full NS access for the moment to use with OS. |
| 64 | */ |
| 65 | INFO("Configuring TrustZone Controller\n"); |
| 66 | |
| 67 | /* |
| 68 | * The driver does some error checking and will assert. |
| 69 | * - Provide base address of device on platform. |
| 70 | * - Provide width of ACE-Lite IDs on platform. |
| 71 | */ |
| 72 | controller.base = TZC400_BASE; |
| 73 | controller.aid_width = FVP_AID_WIDTH; |
| 74 | tzc_init(&controller); |
| 75 | |
| 76 | /* |
| 77 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 78 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 79 | * Filter 1 : not connected |
| 80 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 81 | * Filter 3 : not connected |
| 82 | * Programming unconnected filters will have no effect at the |
| 83 | * moment. These filter could, however, be connected in future. |
| 84 | * So care should be taken not to configure the unused filters. |
| 85 | */ |
| 86 | |
| 87 | /* Disable all filters before programming. */ |
| 88 | tzc_disable_filters(&controller); |
| 89 | |
| 90 | /* |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 91 | * Allow only non-secure access to all DRAM to supported devices. |
| 92 | * Give access to the CPUs and Virtio. Some devices |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 93 | * would normally use the default ID so allow that too. We use |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 94 | * two regions to cover the blocks of physical memory in the FVPs. |
| 95 | * |
| 96 | * Software executing in the secure state, such as a secure |
| 97 | * boot-loader, can access the DRAM by using the NS attributes in |
| 98 | * the MMU translation tables and descriptors. |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 99 | */ |
| 100 | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 101 | /* Set to cover the first block of DRAM */ |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 102 | tzc_configure_region(&controller, FILTER_SHIFT(0), 1, |
Juan Castillo | 7055ca4 | 2014-05-16 15:33:15 +0100 | [diff] [blame^] | 103 | DRAM1_BASE, DRAM1_END - DRAM1_SEC_SIZE, |
| 104 | TZC_REGION_S_NONE, |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 105 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 106 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | |
| 107 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | |
| 108 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | |
| 109 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)); |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 110 | |
Juan Castillo | 7055ca4 | 2014-05-16 15:33:15 +0100 | [diff] [blame^] | 111 | /* Set to cover the secure reserved region */ |
| 112 | tzc_configure_region(&controller, FILTER_SHIFT(0), 3, |
| 113 | (DRAM1_END - DRAM1_SEC_SIZE) + 1 , DRAM1_END, |
| 114 | TZC_REGION_S_RDWR, |
| 115 | 0x0); |
| 116 | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 117 | /* Set to cover the second block of DRAM */ |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 118 | tzc_configure_region(&controller, FILTER_SHIFT(0), 2, |
Juan Castillo | 7055ca4 | 2014-05-16 15:33:15 +0100 | [diff] [blame^] | 119 | DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE, |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 120 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 121 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 122 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 123 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | |
| 124 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)); |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * TODO: Interrupts are not currently supported. The only |
| 128 | * options we have are for access errors to occur quietly or to |
| 129 | * cause an exception. We choose to cause an exception. |
| 130 | */ |
| 131 | tzc_set_action(&controller, TZC_ACTION_ERR); |
| 132 | |
| 133 | /* Enable filters. */ |
| 134 | tzc_enable_filters(&controller); |
| 135 | } |