Haojian Zhuang | 3846f14 | 2017-05-24 08:49:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <cci.h> |
| 10 | #include <debug.h> |
| 11 | #include <gicv2.h> |
| 12 | #include <hi6220.h> |
| 13 | #include <hisi_ipc.h> |
| 14 | #include <hisi_pwrc.h> |
| 15 | #include <hisi_sram_map.h> |
| 16 | #include <mmio.h> |
| 17 | #include <psci.h> |
| 18 | |
| 19 | #include "hikey_def.h" |
| 20 | |
| 21 | #define HIKEY_CLUSTER_STATE_ON 0 |
| 22 | #define HIKEY_CLUSTER_STATE_OFF 1 |
| 23 | |
| 24 | static uintptr_t hikey_sec_entrypoint; |
| 25 | /* There're two clusters in HiKey. */ |
| 26 | static int hikey_cluster_state[] = {HIKEY_CLUSTER_STATE_OFF, |
| 27 | HIKEY_CLUSTER_STATE_OFF}; |
| 28 | |
| 29 | /******************************************************************************* |
| 30 | * Handler called when a power domain is about to be turned on. The |
| 31 | * level and mpidr determine the affinity instance. |
| 32 | ******************************************************************************/ |
| 33 | static int hikey_pwr_domain_on(u_register_t mpidr) |
| 34 | { |
| 35 | int cpu, cluster; |
| 36 | int curr_cluster; |
| 37 | |
| 38 | cluster = MPIDR_AFFLVL1_VAL(mpidr); |
| 39 | cpu = MPIDR_AFFLVL0_VAL(mpidr); |
| 40 | curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); |
| 41 | if (cluster != curr_cluster) |
| 42 | hisi_ipc_cluster_on(cpu, cluster); |
| 43 | |
| 44 | hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); |
| 45 | hisi_ipc_cpu_on(cpu, cluster); |
| 46 | return 0; |
| 47 | } |
| 48 | |
| 49 | static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 50 | { |
| 51 | unsigned long mpidr; |
| 52 | int cpu, cluster; |
| 53 | |
| 54 | mpidr = read_mpidr(); |
| 55 | cluster = MPIDR_AFFLVL1_VAL(mpidr); |
| 56 | cpu = MPIDR_AFFLVL0_VAL(mpidr); |
| 57 | if (hikey_cluster_state[cluster] == HIKEY_CLUSTER_STATE_OFF) { |
| 58 | /* |
| 59 | * Enable CCI coherency for this cluster. |
| 60 | * No need for locks as no other cpu is active at the moment. |
| 61 | */ |
| 62 | cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); |
| 63 | hikey_cluster_state[cluster] = HIKEY_CLUSTER_STATE_ON; |
| 64 | } |
| 65 | |
| 66 | /* Zero the jump address in the mailbox for this cpu */ |
| 67 | hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); |
| 68 | |
| 69 | /* Program the GIC per-cpu distributor or re-distributor interface */ |
| 70 | gicv2_pcpu_distif_init(); |
| 71 | /* Enable the GIC cpu interface */ |
| 72 | gicv2_cpuif_enable(); |
| 73 | } |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * Handler called when a power domain is about to be turned off. The |
| 77 | * target_state encodes the power state that each level should transition to. |
| 78 | ******************************************************************************/ |
| 79 | void hikey_pwr_domain_off(const psci_power_state_t *target_state) |
| 80 | { |
| 81 | unsigned long mpidr; |
| 82 | int cpu, cluster; |
| 83 | |
| 84 | gicv2_cpuif_disable(); |
| 85 | |
| 86 | mpidr = read_mpidr(); |
| 87 | cluster = MPIDR_AFFLVL1_VAL(mpidr); |
| 88 | cpu = MPIDR_AFFLVL0_VAL(mpidr); |
| 89 | if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == |
| 90 | PLAT_MAX_OFF_STATE) { |
| 91 | hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); |
| 92 | cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); |
| 93 | hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); |
| 94 | |
| 95 | hisi_ipc_cluster_off(cpu, cluster); |
| 96 | hikey_cluster_state[cluster] = HIKEY_CLUSTER_STATE_OFF; |
| 97 | } |
| 98 | hisi_ipc_cpu_off(cpu, cluster); |
| 99 | } |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * Handler to reboot the system. |
| 103 | ******************************************************************************/ |
| 104 | static void __dead2 hikey_system_reset(void) |
| 105 | { |
| 106 | /* Send the system reset request */ |
| 107 | mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); |
| 108 | isb(); |
| 109 | dsb(); |
| 110 | |
| 111 | wfi(); |
| 112 | panic(); |
| 113 | } |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * Handler called to check the validity of the power state parameter. |
| 117 | ******************************************************************************/ |
| 118 | int hikey_validate_power_state(unsigned int power_state, |
| 119 | psci_power_state_t *req_state) |
| 120 | { |
| 121 | int pstate = psci_get_pstate_type(power_state); |
| 122 | int pwr_lvl = psci_get_pstate_pwrlvl(power_state); |
| 123 | int i; |
| 124 | |
| 125 | assert(req_state); |
| 126 | |
| 127 | if (pwr_lvl > PLAT_MAX_PWR_LVL) |
| 128 | return PSCI_E_INVALID_PARAMS; |
| 129 | |
| 130 | /* Sanity check the requested state */ |
| 131 | if (pstate == PSTATE_TYPE_STANDBY) { |
| 132 | /* |
| 133 | * It's possible to enter standby only on power level 0 |
| 134 | * Ignore any other power level. |
| 135 | */ |
| 136 | if (pwr_lvl != MPIDR_AFFLVL0) |
| 137 | return PSCI_E_INVALID_PARAMS; |
| 138 | |
| 139 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = |
| 140 | PLAT_MAX_RET_STATE; |
| 141 | } else { |
| 142 | for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) |
| 143 | req_state->pwr_domain_state[i] = |
| 144 | PLAT_MAX_OFF_STATE; |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * We expect the 'state id' to be zero. |
| 149 | */ |
| 150 | if (psci_get_pstate_id(power_state)) |
| 151 | return PSCI_E_INVALID_PARAMS; |
| 152 | |
| 153 | return PSCI_E_SUCCESS; |
| 154 | } |
| 155 | |
| 156 | /******************************************************************************* |
| 157 | * Handler called to check the validity of the non secure entrypoint. |
| 158 | ******************************************************************************/ |
| 159 | static int hikey_validate_ns_entrypoint(uintptr_t entrypoint) |
| 160 | { |
| 161 | /* |
| 162 | * Check if the non secure entrypoint lies within the non |
| 163 | * secure DRAM. |
| 164 | */ |
| 165 | if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) |
| 166 | return PSCI_E_SUCCESS; |
| 167 | |
| 168 | return PSCI_E_INVALID_ADDRESS; |
| 169 | } |
| 170 | |
| 171 | /******************************************************************************* |
| 172 | * Export the platform handlers to enable psci to invoke them |
| 173 | ******************************************************************************/ |
| 174 | static const plat_psci_ops_t hikey_psci_ops = { |
| 175 | .cpu_standby = NULL, |
| 176 | .pwr_domain_on = hikey_pwr_domain_on, |
| 177 | .pwr_domain_on_finish = hikey_pwr_domain_on_finish, |
| 178 | .pwr_domain_off = hikey_pwr_domain_off, |
| 179 | .pwr_domain_suspend = NULL, |
| 180 | .pwr_domain_suspend_finish = NULL, |
| 181 | .system_off = NULL, |
| 182 | .system_reset = hikey_system_reset, |
| 183 | .validate_power_state = hikey_validate_power_state, |
| 184 | .validate_ns_entrypoint = hikey_validate_ns_entrypoint, |
| 185 | .get_sys_suspend_power_state = NULL, |
| 186 | }; |
| 187 | |
| 188 | /******************************************************************************* |
| 189 | * Export the platform specific power ops and initialize Power Controller |
| 190 | ******************************************************************************/ |
| 191 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 192 | const plat_psci_ops_t **psci_ops) |
| 193 | { |
| 194 | hikey_sec_entrypoint = sec_entrypoint; |
| 195 | |
| 196 | /* |
| 197 | * Initialize PSCI ops struct |
| 198 | */ |
| 199 | *psci_ops = &hikey_psci_ops; |
| 200 | |
| 201 | return 0; |
| 202 | } |