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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <arm_def.h>
33#include <bl_common.h>
34#include <console.h>
35#include <platform_def.h>
36#include <plat_arm.h>
37#include <string.h>
38
39
40/*
41 * The next 2 constants identify the extents of the code & RO data region.
42 * These addresses are used by the MMU setup code and therefore they must be
43 * page-aligned. It is the responsibility of the linker script to ensure that
44 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
45 */
46#define BL2_RO_BASE (unsigned long)(&__RO_START__)
47#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
48
49#if USE_COHERENT_MEM
50/*
51 * The next 2 constants identify the extents of the coherent memory region.
52 * These addresses are used by the MMU setup code and therefore they must be
53 * page-aligned. It is the responsibility of the linker script to ensure that
54 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
55 * page-aligned addresses.
56 */
57#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
58#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
59#endif
60
61/* Data structure which holds the extents of the trusted SRAM for BL2 */
62static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
63
64
65/*******************************************************************************
66 * This structure represents the superset of information that is passed to
Juan Castillo7d199412015-12-14 09:35:25 +000067 * BL31, e.g. while passing control to it from BL2, bl31_params
Dan Handley9df48042015-03-19 18:58:55 +000068 * and other platform specific params
69 ******************************************************************************/
70typedef struct bl2_to_bl31_params_mem {
71 bl31_params_t bl31_params;
72 image_info_t bl31_image_info;
73 image_info_t bl32_image_info;
74 image_info_t bl33_image_info;
75 entry_point_info_t bl33_ep_info;
76 entry_point_info_t bl32_ep_info;
77 entry_point_info_t bl31_ep_info;
78} bl2_to_bl31_params_mem_t;
79
80
81static bl2_to_bl31_params_mem_t bl31_params_mem;
82
83
84/* Weak definitions may be overridden in specific ARM standard platform */
85#pragma weak bl2_early_platform_setup
86#pragma weak bl2_platform_setup
87#pragma weak bl2_plat_arch_setup
88#pragma weak bl2_plat_sec_mem_layout
89#pragma weak bl2_plat_get_bl31_params
90#pragma weak bl2_plat_get_bl31_ep_info
91#pragma weak bl2_plat_flush_bl31_params
92#pragma weak bl2_plat_set_bl31_ep_info
Juan Castilloa72b6472015-12-10 15:49:17 +000093#pragma weak bl2_plat_get_scp_bl2_meminfo
Dan Handley9df48042015-03-19 18:58:55 +000094#pragma weak bl2_plat_get_bl32_meminfo
95#pragma weak bl2_plat_set_bl32_ep_info
96#pragma weak bl2_plat_get_bl33_meminfo
97#pragma weak bl2_plat_set_bl33_ep_info
98
99
100meminfo_t *bl2_plat_sec_mem_layout(void)
101{
102 return &bl2_tzram_layout;
103}
104
105/*******************************************************************************
106 * This function assigns a pointer to the memory that the platform has kept
107 * aside to pass platform specific and trusted firmware related information
108 * to BL31. This memory is allocated by allocating memory to
109 * bl2_to_bl31_params_mem_t structure which is a superset of all the
110 * structure whose information is passed to BL31
111 * NOTE: This function should be called only once and should be done
112 * before generating params to BL31
113 ******************************************************************************/
114bl31_params_t *bl2_plat_get_bl31_params(void)
115{
116 bl31_params_t *bl2_to_bl31_params;
117
118 /*
119 * Initialise the memory for all the arguments that needs to
Juan Castillo7d199412015-12-14 09:35:25 +0000120 * be passed to BL31
Dan Handley9df48042015-03-19 18:58:55 +0000121 */
122 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
123
124 /* Assign memory for TF related information */
125 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
126 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
127
Juan Castillo7d199412015-12-14 09:35:25 +0000128 /* Fill BL31 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000129 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
130 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
131 VERSION_1, 0);
132
Juan Castillo7d199412015-12-14 09:35:25 +0000133 /* Fill BL32 related information if it exists */
Dan Handley9df48042015-03-19 18:58:55 +0000134#if BL32_BASE
135 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
136 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
137 VERSION_1, 0);
138 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
139 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
140 VERSION_1, 0);
141#endif
142
Juan Castillo7d199412015-12-14 09:35:25 +0000143 /* Fill BL33 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000144 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
145 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
146 PARAM_EP, VERSION_1, 0);
147
Juan Castillo7d199412015-12-14 09:35:25 +0000148 /* BL33 expects to receive the primary CPU MPID (through x0) */
Dan Handley9df48042015-03-19 18:58:55 +0000149 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
150
151 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
152 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
153 VERSION_1, 0);
154
155 return bl2_to_bl31_params;
156}
157
158/* Flush the TF params and the TF plat params */
159void bl2_plat_flush_bl31_params(void)
160{
161 flush_dcache_range((unsigned long)&bl31_params_mem,
162 sizeof(bl2_to_bl31_params_mem_t));
163}
164
165/*******************************************************************************
166 * This function returns a pointer to the shared memory that the platform
167 * has kept to point to entry point information of BL31 to BL2
168 ******************************************************************************/
169struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
170{
171#if DEBUG
172 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL;
173#endif
174
175 return &bl31_params_mem.bl31_ep_info;
176}
177
178/*******************************************************************************
179 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
180 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
181 * Copy it to a safe location before its reclaimed by later BL2 functionality.
182 ******************************************************************************/
183void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
184{
185 /* Initialize the console to provide early debug support */
186 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
187 ARM_CONSOLE_BAUDRATE);
188
189 /* Setup the BL2 memory layout */
190 bl2_tzram_layout = *mem_layout;
191
192 /* Initialise the IO layer and register platform IO devices */
193 plat_arm_io_setup();
194}
195
196void bl2_early_platform_setup(meminfo_t *mem_layout)
197{
198 arm_bl2_early_platform_setup(mem_layout);
199}
200
201/*
202 * Perform ARM standard platform setup.
203 */
204void arm_bl2_platform_setup(void)
205{
206 /* Initialize the secure environment */
207 plat_arm_security_setup();
208}
209
210void bl2_platform_setup(void)
211{
212 arm_bl2_platform_setup();
213}
214
215/*******************************************************************************
216 * Perform the very early platform specific architectural setup here. At the
217 * moment this is only initializes the mmu in a quick and dirty way.
218 ******************************************************************************/
219void arm_bl2_plat_arch_setup(void)
220{
221 arm_configure_mmu_el1(bl2_tzram_layout.total_base,
222 bl2_tzram_layout.total_size,
223 BL2_RO_BASE,
224 BL2_RO_LIMIT
225#if USE_COHERENT_MEM
226 , BL2_COHERENT_RAM_BASE,
227 BL2_COHERENT_RAM_LIMIT
228#endif
229 );
230}
231
232void bl2_plat_arch_setup(void)
233{
234 arm_bl2_plat_arch_setup();
235}
236
237/*******************************************************************************
Juan Castilloa72b6472015-12-10 15:49:17 +0000238 * Populate the extents of memory available for loading SCP_BL2 (if used),
Dan Handley9df48042015-03-19 18:58:55 +0000239 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
240 ******************************************************************************/
Juan Castilloa72b6472015-12-10 15:49:17 +0000241void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
Dan Handley9df48042015-03-19 18:58:55 +0000242{
Juan Castilloa72b6472015-12-10 15:49:17 +0000243 *scp_bl2_meminfo = bl2_tzram_layout;
Dan Handley9df48042015-03-19 18:58:55 +0000244}
245
246/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000247 * Before calling this function BL31 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000248 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000249 * the entrypoint of BL31 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000250 * On ARM standard platforms we only set the security state of the entrypoint
251 ******************************************************************************/
252void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
253 entry_point_info_t *bl31_ep_info)
254{
255 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
256 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
257 DISABLE_ALL_EXCEPTIONS);
258}
259
260
261/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000262 * Before calling this function BL32 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000263 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000264 * the entrypoint of BL32 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000265 * On ARM standard platforms we only set the security state of the entrypoint
266 ******************************************************************************/
267void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
268 entry_point_info_t *bl32_ep_info)
269{
270 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
271 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
272}
273
274/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000275 * Before calling this function BL33 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000276 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000277 * the entrypoint of BL33 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000278 * On ARM standard platforms we only set the security state of the entrypoint
279 ******************************************************************************/
280void bl2_plat_set_bl33_ep_info(image_info_t *image,
281 entry_point_info_t *bl33_ep_info)
282{
283
284 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
285 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
286}
287
288/*******************************************************************************
289 * Populate the extents of memory available for loading BL32
290 ******************************************************************************/
291void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
292{
293 /*
294 * Populate the extents of memory available for loading BL32.
295 */
296 bl32_meminfo->total_base = BL32_BASE;
297 bl32_meminfo->free_base = BL32_BASE;
298 bl32_meminfo->total_size =
299 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
300 bl32_meminfo->free_size =
301 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
302}
303
304
305/*******************************************************************************
306 * Populate the extents of memory available for loading BL33
307 ******************************************************************************/
308void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
309{
310 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
311 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
312 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
313 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
314}