blob: 77b3c6179b6b2a0bd77f417f2670fa6c7de99d5a [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +02001#
2# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7ifeq (${RCAR_LSI},${RCAR_AUTO})
8# E3, H3N not available for LSI_AUTO
9 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
10 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
11 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
12 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
13 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
14 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Marek Vasut3af20052019-02-25 14:57:08 +010015 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020016 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
17else ifdef RCAR_LSI_CUT_COMPAT
18 ifeq (${RCAR_LSI},${RCAR_H3})
19 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
20 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
21 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
22 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
23 endif
24 ifeq (${RCAR_LSI},${RCAR_H3N})
25 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
26 endif
27 ifeq (${RCAR_LSI},${RCAR_M3})
28 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
29 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Marek Vasut3af20052019-02-25 14:57:08 +010030 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020031 endif
32 ifeq (${RCAR_LSI},${RCAR_M3N})
33 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
34 endif
35 ifeq (${RCAR_LSI},${RCAR_E3})
36 BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
37 endif
Marek Vasut6f39e3c2018-06-14 06:26:45 +020038 ifeq (${RCAR_LSI},${RCAR_D3})
39 BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
40 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020041else
42 ifeq (${RCAR_LSI},${RCAR_H3})
43 ifeq (${LSI_CUT},10)
44 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
45 else ifeq (${LSI_CUT},11)
46 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
47 else ifeq (${LSI_CUT},20)
48 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
49 else ifeq (${LSI_CUT},30)
50 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
51 else
52# LSI_CUT 30 or later
53 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
54 endif
55 endif
56 ifeq (${RCAR_LSI},${RCAR_H3N})
57 ifeq (${LSI_CUT},30)
58 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
59 else
60# LSI_CUT 30 or later
61 BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
62 endif
63 endif
64 ifeq (${RCAR_LSI},${RCAR_M3})
65 ifeq (${LSI_CUT},10)
66 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
67 else ifeq (${LSI_CUT},11)
68 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Marek Vasut3af20052019-02-25 14:57:08 +010069 else ifeq (${LSI_CUT},13)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020070 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Marek Vasut3af20052019-02-25 14:57:08 +010071 else ifeq (${LSI_CUT},30)
72 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
73 else
74# LSI_CUT 30 or later
75 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020076 endif
77 endif
78 ifeq (${RCAR_LSI},${RCAR_M3N})
79 ifeq (${LSI_CUT},10)
80 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
81 else
82# LSI_CUT 10 or later
83 BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
84 endif
85 endif
86 ifeq (${RCAR_LSI},${RCAR_E3})
87 ifeq (${LSI_CUT},10)
88 BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
89 else
90# LSI_CUT 10 or later
91 BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
92 endif
93 endif
Marek Vasut6f39e3c2018-06-14 06:26:45 +020094 ifeq (${RCAR_LSI},${RCAR_D3})
95 BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
96 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020097endif
98
99BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c