| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A17_H |
| 8 | #define CORTEX_A17_H |
| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 12 | /******************************************************************************* |
| 13 | * Cortex-A17 midr with version/revision set to 0 |
| 14 | ******************************************************************************/ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 15 | #define CORTEX_A17_MIDR U(0x410FC0E0) |
| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 16 | |
| 17 | /******************************************************************************* |
| 18 | * CPU Auxiliary Control register specific definitions. |
| 19 | ******************************************************************************/ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 20 | #define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6) |
| Etienne Carriere | 010dd1f | 2017-11-05 22:56:41 +0100 | [diff] [blame] | 21 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 22 | #endif /* CORTEX_A17_H */ |