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git01.mediatek.com / filogic / atf / 6ed3bf61eb9bf3adb58ee6de6832faf6823b6aad / . / include / drivers / nxp / trdc / imx_trdc.h
blob: 0b41fcf451ac444800b7fc9982010b359e49c717 [file] [log] [blame]
Jacky Baief29c152023-05-25 09:34:11 +0800[diff] [blame]1/*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef IMX_TRDC_H
8#define IMX_XRDC_H
9
10#define MBC_BLK_ALL U(255)
11#define MRC_REG_ALL U(16)
12#define GLBAC_NUM U(8)
13
14#define DID_NUM U(16)
15#define MBC_MAX_NUM U(4)
16#define MRC_MAX_NUM U(2)
17#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
18#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
19
20#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF)
21#define MRC_RGN_NUM(GLBCFG) ((GLBCFG) & 0x1F)
22
23#define MDAC_W_X(m, r) (0x800 + (m) * 0x20 + (r) * 0x4)
24
25/* CPU/non-CPU domain common bits */
26#define MDA_VLD BIT(31)
27#define MDA_LK1 BIT(30)
28#define MDA_DFMT BIT(29)
29
30/* CPU domain bits */
31#define MDA_DFMT0_DID(x) ((x) & 0xF)
32#define MDA_DFMT0_DIDS(x) (((x) & 0x3) << 4)
33#define MDA_DFMT0_PE(x) (((x) & 0x3) << 6)
34#define MDA_DFMT0_PIDM(x) (((x) & 0x3F) << 8)
35#define MDA_DFMT0_SA(x) (((x) & 0x3) << 14)
36#define MDA_DFMT0_PID(x) (((x) & 0x3F) << 16)
37
38/* non-CPU domain bits */
39#define MDA_DFMT1_DID(x) ((x) & 0xF)
40#define MDA_DFMT1_PA(x) (((x) & 0x3) << 4)
41#define MDA_DFMT1_SA(x) (((x) & 0x3) << 6)
42#define MDA_DFMT1_DIDB(x) ((x) << 8)
43
44#define SP(X) ((X) << 12)
45#define SU(X) ((X) << 8)
46#define NP(X) ((X) << 4)
47#define NU(X) ((X) << 0)
48
49#define RWX U(7)
50#define RW U(6)
51#define RX U(5)
52#define R U(4)
53#define X U(1)
54
55struct mbc_mem_dom {
56 uint32_t mem_glbcfg[4];
57 uint32_t nse_blk_index;
58 uint32_t nse_blk_set;
59 uint32_t nse_blk_clr;
60 uint32_t nsr_blk_clr_all;
61 uint32_t memn_glbac[8];
62 /* The upper only existed in the beginning of each MBC */
63 uint32_t mem0_blk_cfg_w[64];
64 uint32_t mem0_blk_nse_w[16];
65 uint32_t mem1_blk_cfg_w[8];
66 uint32_t mem1_blk_nse_w[2];
67 uint32_t mem2_blk_cfg_w[8];
68 uint32_t mem2_blk_nse_w[2];
69 uint32_t mem3_blk_cfg_w[8];
70 uint32_t mem3_blk_nse_w[2]; /*0x1F0, 0x1F4 */
71 uint32_t reserved[2];
72};
73
74struct mrc_rgn_dom {
75 uint32_t mrc_glbcfg[4];
76 uint32_t nse_rgn_indirect;
77 uint32_t nse_rgn_set;
78 uint32_t nse_rgn_clr;
79 uint32_t nse_rgn_clr_all;
80 uint32_t memn_glbac[8];
81 /* The upper only existed in the beginning of each MRC */
82 uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
83 uint32_t rgn_nse;
84 uint32_t reserved2[15];
85};
86
87struct mda_inst {
88 uint32_t mda_w[8];
89};
90
91struct trdc_mgr {
92 uint32_t trdc_cr;
93 uint32_t res0[59];
94 uint32_t trdc_hwcfg0;
95 uint32_t trdc_hwcfg1;
96 uint32_t res1[450];
97 struct mda_inst mda[128];
98};
99
100struct trdc_mbc {
101 struct mbc_mem_dom mem_dom[DID_NUM];
102};
103
104struct trdc_mrc {
105 struct mrc_rgn_dom mrc_dom[DID_NUM];
106};
107
108/***************************************************************
109 * Below structs used fro provding the TRDC configuration info
110 * that will be used to init the TRDC based on use case.
111 ***************************************************************/
112struct trdc_glbac_config {
113 uint8_t mbc_mrc_id;
114 uint8_t glbac_id;
115 uint32_t glbac_val;
116};
117
118struct trdc_mbc_config {
119 uint8_t mbc_id;
120 uint8_t dom_id;
121 uint8_t mem_id;
122 uint8_t blk_id;
123 uint8_t glbac_id;
124 bool secure;
125};
126
127struct trdc_mrc_config {
128 uint8_t mrc_id;
129 uint8_t dom_id;
130 uint8_t region_id;
131 uint32_t region_start;
132 uint32_t region_size;
133 uint8_t glbac_id;
134 bool secure;
135};
136
137struct trdc_mgr_info {
138 uintptr_t trdc_base;
139 uint8_t mbc_id;
140 uint8_t mbc_mem_id;
141 uint8_t blk_mgr;
142 uint8_t blk_mc;
143};
144
145struct trdc_config_info {
146 uintptr_t trdc_base;
147 struct trdc_glbac_config *mbc_glbac;
148 uint32_t num_mbc_glbac;
149 struct trdc_mbc_config *mbc_cfg;
150 uint32_t num_mbc_cfg;
151 struct trdc_glbac_config *mrc_glbac;
152 uint32_t num_mrc_glbac;
153 struct trdc_mrc_config *mrc_cfg;
154 uint32_t num_mrc_cfg;
155};
156
157extern struct trdc_mgr_info trdc_mgr_blks[];
158extern unsigned int trdc_mgr_num;
159/* APIs to apply and enable TRDC */
160int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst,
161 uint32_t mda_reg, uint8_t sa, uint8_t dids,
162 uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid);
163
164int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst,
165 bool did_bypass, uint8_t sa, uint8_t pa,
166 uint8_t did);
167
168void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr);
169void trdc_setup(struct trdc_config_info *cfg);
170void trdc_config(void);
171
172#endif /* IMX_TRDC_H */