| Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 15 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 18 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 19 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 20 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 21 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 22 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 23 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 24 | * POSSIBILITY OF SUCH DAMAGE. |
| 25 | */ |
| 26 | |
| 27 | #include <arch.h> |
| 28 | #include <asm_macros.S> |
| 29 | #include <platform_def.h> |
| 30 | #include <pmu_sram.h> |
| 31 | |
| 32 | .globl pmu_cpuson_entrypoint_start |
| 33 | .globl pmu_cpuson_entrypoint_end |
| 34 | |
| 35 | func pmu_cpuson_entrypoint |
| 36 | pmu_cpuson_entrypoint_start: |
| 37 | ldr x5, psram_data |
| 38 | ldr w0, [x5, #PSRAM_DT_SYS_MODE] |
| 39 | cmp w0, #PMU_SYS_SLP_MODE |
| 40 | b.eq check_wake_cpus |
| 41 | ldr x6, warm_boot_func |
| 42 | br x6 |
| 43 | check_wake_cpus: |
| 44 | mrs x0, MPIDR_EL1 |
| 45 | and x1, x0, #MPIDR_CPU_MASK |
| 46 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 47 | orr x0, x0, x1 |
| 48 | /* primary_cpu */ |
| 49 | ldr w1, [x5, #PSRAM_DT_MPIDR] |
| 50 | cmp w0, w1 |
| 51 | b.eq sys_wakeup |
| 52 | /* |
| 53 | * If the core is not the primary cpu, |
| 54 | * force the core into wfe. |
| 55 | */ |
| 56 | wfe_loop: |
| 57 | wfe |
| 58 | b wfe_loop |
| 59 | sys_wakeup: |
| 60 | /* check ddr flag for resume ddr */ |
| 61 | ldr w2, [x5, #PSRAM_DT_DDRFLAG] |
| 62 | cmp w2, #0x0 |
| 63 | b.eq sys_resume |
| 64 | ddr_resume: |
| 65 | ldr x2, [x5, #PSRAM_DT_SP] |
| 66 | mov sp, x2 |
| 67 | ldr x1, [x5, #PSRAM_DT_DDR_FUNC] |
| 68 | ldr x0, [x5, #PSRAM_DT_DDR_DATA] |
| 69 | blr x1 |
| 70 | sys_resume: |
| 71 | ldr x1, sys_wakeup_entry |
| 72 | br x1 |
| 73 | |
| 74 | .align 3 |
| 75 | psram_data: |
| 76 | .quad PSRAM_DT_BASE |
| 77 | warm_boot_func: |
| 78 | .quad platform_cpu_warmboot |
| 79 | sys_wakeup_entry: |
| 80 | .quad psci_entrypoint |
| 81 | pmu_cpuson_entrypoint_end: |
| 82 | .word 0 |
| 83 | endfunc pmu_cpuson_entrypoint |