blob: 9053728872f18fc6f6baf86bbc2f14173ec71c14 [file] [log] [blame]
Andre Przywara13815472018-06-01 02:01:39 +01001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <mmio.h>
9#include <sunxi_mmap.h>
Andre Przywara456208a2018-10-14 12:02:02 +010010#include <sunxi_private.h>
Andre Przywara13815472018-06-01 02:01:39 +010011
12#ifdef SUNXI_SPC_BASE
13#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
14#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
15#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
16#endif
17
18#define R_PRCM_SEC_SWITCH_REG 0x1d0
19#define DMA_SEC_REG 0x20
20
21/*
22 * Setup the peripherals to be accessible by non-secure world.
23 * This will not work for the Secure Peripherals Controller (SPC) unless
24 * a fuse it burnt (seems to be an erratum), but we do it nevertheless,
25 * to allow booting on boards using secure boot.
26 */
27void sunxi_security_setup(void)
28{
Andre Przywarabd60b022018-06-22 00:28:31 +010029#ifdef SUNXI_SPC_BASE
Andre Przywara13815472018-06-01 02:01:39 +010030 int i;
31
Andre Przywara13815472018-06-01 02:01:39 +010032 INFO("Configuring SPC Controller\n");
33 /* SPC setup: set all devices to non-secure */
34 for (i = 0; i < 6; i++)
35 mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
36#endif
37
38 /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
39 mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
40
41 /* set R_PRCM clocks to non-secure */
42 mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x7);
43
44 /* Set all DMA channels (16 max.) to non-secure */
45 mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
46}