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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
Prasad Kummari877efa72023-10-31 15:05:29 +05303 * Copyright (c) 2023, Advanced Micro Devices. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/bl_common.h>
9#include <common/debug.h>
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053010#include <drivers/arm/pl011.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <drivers/console.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000012#include <plat/arm/common/plat_arm.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010013#include <platform_tsp.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014
Prasad Kummari536e1102023-06-22 10:50:02 +053015#include <plat_private.h>
16
Soren Brinkmann76fcae32016-03-06 20:16:27 -080017/*******************************************************************************
18 * Initialize the UART
19 ******************************************************************************/
20void tsp_early_platform_setup(void)
21{
22 /*
Ambroise Vincent53f193f2019-05-29 11:46:08 +010023 * Register a different console than already in use to display
Soren Brinkmann76fcae32016-03-06 20:16:27 -080024 * messages from TSP
25 */
Andre Przywara8ccc4a42020-01-25 00:58:35 +000026 static console_t tsp_boot_console;
Prasad Kummari877efa72023-10-31 15:05:29 +053027 int32_t rc;
28
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053029#if defined(PLAT_zynqmp)
Prasad Kummari877efa72023-10-31 15:05:29 +053030 rc = console_cdns_register((uintptr_t)UART_BASE,
31 (uint32_t)get_uart_clk(),
32 (uint32_t)UART_BAUDRATE,
33 &tsp_boot_console);
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053034#else
35 rc = console_pl011_register((uintptr_t)UART_BASE,
36 (uint32_t)get_uart_clk(),
37 (uint32_t)UART_BAUDRATE,
38 &tsp_boot_console);
39#endif
40
Prasad Kummari877efa72023-10-31 15:05:29 +053041 if (rc == 0) {
42 panic();
43 }
44
Andre Przywara8ccc4a42020-01-25 00:58:35 +000045 console_set_scope(&tsp_boot_console,
Ambroise Vincent53f193f2019-05-29 11:46:08 +010046 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080047}
48
49/*******************************************************************************
50 * Perform platform specific setup placeholder
51 ******************************************************************************/
52void tsp_platform_setup(void)
53{
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053054/*
55 * For ZynqMP, the GICv2 driver needs to be initialized in S-EL1,
56 * and for other platforms, the GICv3 driver is initialized in EL3.
57 * This is because S-EL1 can use GIC system registers to manage
58 * interrupts and does not need to be initialized again in SEL1.
59 */
60#if defined(PLAT_zynqmp)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080061 plat_arm_gic_driver_init();
62 plat_arm_gic_init();
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053063#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080064}
65
66/*******************************************************************************
67 * Perform the very early platform specific architectural setup here. At the
Elyes Haouas2be03c02023-02-13 09:14:48 +010068 * moment this is only initializes the MMU
Soren Brinkmann76fcae32016-03-06 20:16:27 -080069 ******************************************************************************/
70void tsp_plat_arch_setup(void)
71{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010072 const mmap_region_t bl_regions[] = {
73 MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE,
74 MT_MEMORY | MT_RW | MT_SECURE),
75 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
76 MT_CODE | MT_SECURE),
77 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
78 MT_RO_DATA | MT_SECURE),
79 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
80 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
81 MT_DEVICE | MT_RW | MT_SECURE),
82 {0}
83 };
84
Prasad Kummari0b377142023-10-26 16:32:26 +053085 setup_page_tables(bl_regions, plat_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010086 enable_mmu_el1(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080087}