| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A32_H |
| 8 | #define CORTEX_A32_H |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 12 | /* Cortex-A32 Main ID register for revision 0 */ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A32_MIDR U(0x410FD010) |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | * CPUECTLR_EL1 is an implementation-specific register. |
| 18 | ******************************************************************************/ |
| 19 | #define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15 |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 20 | #define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6) |
| Yatharth Kochar | a4c219a | 2016-07-12 15:47:03 +0100 | [diff] [blame] | 21 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 22 | #endif /* CORTEX_A32_H */ |