Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 32 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 33 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 34 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 35 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 36 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 38 | /* --------------------------------------------- |
| 39 | * Disable L1 data cache and unified L2 cache |
| 40 | * --------------------------------------------- |
| 41 | */ |
| 42 | func cortex_a53_disable_dcache |
| 43 | mrs x1, sctlr_el3 |
| 44 | bic x1, x1, #SCTLR_C_BIT |
| 45 | msr sctlr_el3, x1 |
| 46 | isb |
| 47 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 48 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 49 | |
| 50 | /* --------------------------------------------- |
| 51 | * Disable intra-cluster coherency |
| 52 | * --------------------------------------------- |
| 53 | */ |
| 54 | func cortex_a53_disable_smp |
| 55 | mrs x0, CPUECTLR_EL1 |
| 56 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 57 | msr CPUECTLR_EL1, x0 |
| 58 | isb |
| 59 | dsb sy |
| 60 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 61 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 63 | /* -------------------------------------------------- |
| 64 | * Errata Workaround for Cortex A53 Errata #826319. |
| 65 | * This applies only to revision <= r0p2 of Cortex A53. |
| 66 | * Inputs: |
| 67 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 68 | * Clobbers : x0 - x5 |
| 69 | * -------------------------------------------------- |
| 70 | */ |
| 71 | func errata_a53_826319_wa |
| 72 | /* |
| 73 | * Compare x0 against revision r0p2 |
| 74 | */ |
| 75 | cmp x0, #2 |
| 76 | b.ls apply_826319 |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 77 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 78 | b print_revision_warning |
| 79 | #else |
| 80 | ret |
| 81 | #endif |
| 82 | apply_826319: |
| 83 | mrs x1, L2ACTLR_EL1 |
| 84 | bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN |
| 85 | orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH |
| 86 | msr L2ACTLR_EL1, x1 |
| 87 | ret |
| 88 | endfunc errata_a53_826319_wa |
| 89 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 90 | /* --------------------------------------------------------------------- |
| 91 | * Disable the cache non-temporal hint. |
| 92 | * |
| 93 | * This ignores the Transient allocation hint in the MAIR and treats |
| 94 | * allocations the same as non-transient allocation types. As a result, |
| 95 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 96 | * equivalent LDP and STP instructions. |
| 97 | * |
| 98 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 99 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 100 | * default at reset. |
| 101 | * |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 102 | * Inputs: |
| 103 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 104 | * Clobbers : x0 - x5 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 105 | * --------------------------------------------------------------------- |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 106 | */ |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 107 | func a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 108 | /* |
| 109 | * Compare x0 against revision r0p3 |
| 110 | */ |
| 111 | cmp x0, #3 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 112 | b.ls disable_hint |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 113 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 114 | b print_revision_warning |
| 115 | #else |
| 116 | ret |
| 117 | #endif |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 118 | disable_hint: |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 119 | mrs x1, CPUACTLR_EL1 |
| 120 | orr x1, x1, #CPUACTLR_DTAH |
| 121 | msr CPUACTLR_EL1, x1 |
| 122 | ret |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 123 | endfunc a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 124 | |
| 125 | /* ------------------------------------------------- |
| 126 | * The CPU Ops reset function for Cortex-A53. |
| 127 | * Clobbers: x0-x5, x15, x19, x30 |
| 128 | * ------------------------------------------------- |
| 129 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 130 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 131 | mov x19, x30 |
| 132 | mrs x0, midr_el1 |
| 133 | |
| 134 | /* |
| 135 | * Extract the variant[20:23] and revision[0:3] from x0 |
| 136 | * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. |
| 137 | * First extract x0[16:23] to x15[0:7] and zero fill the rest. |
| 138 | * Then extract x0[0:3] into x15[0:3] retaining other bits. |
| 139 | */ |
| 140 | ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ |
| 141 | #(MIDR_REV_BITS + MIDR_VAR_BITS) |
| 142 | bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS |
| 143 | |
| 144 | #if ERRATA_A53_826319 |
| 145 | mov x0, x15 |
| 146 | bl errata_a53_826319_wa |
| 147 | #endif |
| 148 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 149 | #if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 150 | mov x0, x15 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 151 | bl a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 152 | #endif |
| 153 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 155 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 156 | * --------------------------------------------- |
| 157 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 158 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 159 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 160 | msr CPUECTLR_EL1, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 161 | isb |
| 162 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 163 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 164 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 165 | func cortex_a53_core_pwr_dwn |
| 166 | mov x18, x30 |
| 167 | |
| 168 | /* --------------------------------------------- |
| 169 | * Turn off caches. |
| 170 | * --------------------------------------------- |
| 171 | */ |
| 172 | bl cortex_a53_disable_dcache |
| 173 | |
| 174 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 175 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 176 | * --------------------------------------------- |
| 177 | */ |
| 178 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 179 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 180 | |
| 181 | /* --------------------------------------------- |
| 182 | * Come out of intra cluster coherency |
| 183 | * --------------------------------------------- |
| 184 | */ |
| 185 | mov x30, x18 |
| 186 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 187 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 188 | |
| 189 | func cortex_a53_cluster_pwr_dwn |
| 190 | mov x18, x30 |
| 191 | |
| 192 | /* --------------------------------------------- |
| 193 | * Turn off caches. |
| 194 | * --------------------------------------------- |
| 195 | */ |
| 196 | bl cortex_a53_disable_dcache |
| 197 | |
| 198 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 199 | * Flush L1 caches. |
| 200 | * --------------------------------------------- |
| 201 | */ |
| 202 | mov x0, #DCCISW |
| 203 | bl dcsw_op_level1 |
| 204 | |
| 205 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 206 | * Disable the optional ACP. |
| 207 | * --------------------------------------------- |
| 208 | */ |
| 209 | bl plat_disable_acp |
| 210 | |
| 211 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 212 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 213 | * --------------------------------------------- |
| 214 | */ |
| 215 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 216 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 217 | |
| 218 | /* --------------------------------------------- |
| 219 | * Come out of intra cluster coherency |
| 220 | * --------------------------------------------- |
| 221 | */ |
| 222 | mov x30, x18 |
| 223 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 224 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 225 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 226 | /* --------------------------------------------- |
| 227 | * This function provides cortex_a53 specific |
| 228 | * register information for crash reporting. |
| 229 | * It needs to return with x6 pointing to |
| 230 | * a list of register names in ascii and |
| 231 | * x8 - x15 having values of registers to be |
| 232 | * reported. |
| 233 | * --------------------------------------------- |
| 234 | */ |
| 235 | .section .rodata.cortex_a53_regs, "aS" |
| 236 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
| 237 | .asciz "cpuectlr_el1", "" |
| 238 | |
| 239 | func cortex_a53_cpu_reg_dump |
| 240 | adr x6, cortex_a53_regs |
| 241 | mrs x8, CPUECTLR_EL1 |
| 242 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 243 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 244 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 245 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR |