Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <context.h> |
| 12 | #include <lib/el3_runtime/context_mgmt.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <denver.h> |
| 15 | #include <mce.h> |
| 16 | #include <mce_private.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 17 | #include <platform_def.h> |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 18 | #include <stdbool.h> |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 19 | #include <stdint.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 20 | #include <string.h> |
| 21 | #include <errno.h> |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 22 | #include <inttypes.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 23 | #include <t194_nvg.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 24 | #include <tegra_def.h> |
| 25 | #include <tegra_platform.h> |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 26 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 27 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 28 | /* Handler to check if MCE firmware is supported */ |
| 29 | static bool mce_firmware_not_supported(void) |
| 30 | { |
| 31 | bool status; |
| 32 | |
| 33 | /* these platforms do not load MCE firmware */ |
| 34 | status = tegra_platform_is_linsim() || tegra_platform_is_qt() || |
| 35 | tegra_platform_is_virt_dev_kit(); |
| 36 | |
| 37 | return status; |
| 38 | } |
| 39 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 40 | /******************************************************************************* |
| 41 | * Common handler for all MCE commands |
| 42 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 43 | int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 44 | uint64_t arg2) |
| 45 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 46 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 47 | |
| 48 | switch (cmd) { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 49 | case (uint64_t)MCE_CMD_ENTER_CSTATE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 50 | ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); |
| 51 | if (ret < 0) { |
| 52 | ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); |
| 53 | } |
| 54 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 55 | break; |
| 56 | |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 57 | case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 58 | ret = nvg_is_sc7_allowed(); |
| 59 | if (ret < 0) { |
| 60 | ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 61 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 62 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 63 | break; |
| 64 | |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 65 | case (uint64_t)MCE_CMD_ONLINE_CORE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 66 | ret = nvg_online_core((uint32_t)arg0); |
| 67 | if (ret < 0) { |
| 68 | ERROR("%s: online_core failed(%d)\n", __func__, ret); |
| 69 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 70 | |
| 71 | break; |
| 72 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 73 | default: |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 74 | ERROR("unknown MCE command (%" PRIu64 ")\n", cmd); |
Varun Wadekar | 7aa6c03 | 2017-10-19 12:02:17 -0700 | [diff] [blame] | 75 | ret = -EINVAL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 76 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | return ret; |
| 80 | } |
| 81 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 82 | /******************************************************************************* |
| 83 | * Handler to update carveout values for Video Memory Carveout region |
| 84 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 85 | int32_t mce_update_gsc_videomem(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 86 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 87 | int32_t ret; |
| 88 | |
| 89 | /* |
| 90 | * MCE firmware is not running on simulation platforms. |
| 91 | */ |
| 92 | if (mce_firmware_not_supported()) { |
| 93 | ret = -EINVAL; |
| 94 | } else { |
| 95 | ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR); |
| 96 | } |
| 97 | |
| 98 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * Handler to update carveout values for TZDRAM aperture |
| 103 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 104 | int32_t mce_update_gsc_tzdram(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 105 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 106 | int32_t ret; |
| 107 | |
| 108 | /* |
| 109 | * MCE firmware is not running on simulation platforms. |
| 110 | */ |
| 111 | if (mce_firmware_not_supported()) { |
| 112 | ret = -EINVAL; |
| 113 | } else { |
| 114 | ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM); |
| 115 | } |
| 116 | |
| 117 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 121 | * Handler to issue the UPDATE_CSTATE_INFO request |
| 122 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 123 | void mce_update_cstate_info(const mce_cstate_info_t *cstate) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 124 | { |
| 125 | /* issue the UPDATE_CSTATE_INFO request */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 126 | nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, |
| 127 | cstate->wake_mask, cstate->update_wake_mask); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | /******************************************************************************* |
| 131 | * Handler to read the MCE firmware version and check if it is compatible |
| 132 | * with interface header the BL3-1 was compiled against |
| 133 | ******************************************************************************/ |
| 134 | void mce_verify_firmware_version(void) |
| 135 | { |
| 136 | uint64_t version; |
| 137 | uint32_t major, minor; |
| 138 | |
| 139 | /* |
| 140 | * MCE firmware is not running on simulation platforms. |
| 141 | */ |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 142 | if (mce_firmware_not_supported()) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 143 | return; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 144 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * Read the MCE firmware version and extract the major and minor |
| 148 | * version fields |
| 149 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 150 | version = nvg_get_version(); |
| 151 | minor = (uint32_t)version; |
| 152 | major = (uint32_t)(version >> 32); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 153 | |
Varun Wadekar | 093bfaa | 2017-11-07 08:50:55 -0800 | [diff] [blame] | 154 | INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor, |
| 155 | TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 156 | |
| 157 | /* |
| 158 | * Verify that the MCE firmware version and the interface header |
| 159 | * match |
| 160 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 161 | if (major != (uint32_t)TEGRA_NVG_VERSION_MAJOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 162 | ERROR("MCE major version mismatch\n"); |
| 163 | panic(); |
| 164 | } |
| 165 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 166 | if (minor < (uint32_t)TEGRA_NVG_VERSION_MINOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 167 | ERROR("MCE minor version mismatch\n"); |
| 168 | panic(); |
| 169 | } |
| 170 | } |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 171 | |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 172 | #if ENABLE_STRICT_CHECKING_MODE |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 173 | /******************************************************************************* |
| 174 | * Handler to enable the strict checking mode |
| 175 | ******************************************************************************/ |
| 176 | void mce_enable_strict_checking(void) |
| 177 | { |
| 178 | uint64_t sctlr = read_sctlr_el3(); |
| 179 | int32_t ret = 0; |
| 180 | |
| 181 | if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { |
| 182 | /* |
| 183 | * Step1: TZ-DRAM and TZRAM should be setup before the MMU is |
| 184 | * enabled. |
| 185 | * |
| 186 | * The common code makes sure that TZDRAM/TZRAM are already |
| 187 | * enabled before calling into this handler. If this is not the |
| 188 | * case, the following sequence must be executed before moving |
| 189 | * on to step 2. |
| 190 | * |
| 191 | * tlbialle1is(); |
| 192 | * tlbialle3is(); |
| 193 | * dsbsy(); |
| 194 | * isb(); |
| 195 | * |
| 196 | */ |
| 197 | if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) { |
| 198 | tlbialle1is(); |
| 199 | tlbialle3is(); |
| 200 | dsbsy(); |
| 201 | isb(); |
| 202 | } |
| 203 | |
| 204 | /* |
| 205 | * Step2: SCF flush - Clean and invalidate caches and clear the |
| 206 | * TR-bits |
| 207 | */ |
| 208 | ret = nvg_roc_clean_cache_trbits(); |
| 209 | if (ret < 0) { |
| 210 | ERROR("%s: flush cache_trbits failed(%d)\n", __func__, |
| 211 | ret); |
| 212 | return; |
| 213 | } |
| 214 | |
| 215 | /* |
| 216 | * Step3: Issue the SECURITY_CONFIG request to MCE to enable |
| 217 | * strict checking mode. |
| 218 | */ |
| 219 | nvg_enable_strict_checking_mode(); |
| 220 | } |
| 221 | } |
Anthony Zhou | 10b970c | 2020-02-05 20:42:36 +0800 | [diff] [blame] | 222 | void mce_verify_strict_checking(void) |
| 223 | { |
| 224 | bool is_silicon = tegra_platform_is_silicon(); |
| 225 | bool is_fpga = tegra_platform_is_fpga(); |
| 226 | |
| 227 | if (is_silicon || is_fpga) { |
| 228 | nvg_verify_strict_checking_mode(); |
| 229 | } |
| 230 | } |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 231 | #endif |
Vignesh Radhakrishnan | 3ad7983 | 2017-12-11 13:17:58 -0800 | [diff] [blame] | 232 | |
| 233 | /******************************************************************************* |
| 234 | * Handler to power down the entire system |
| 235 | ******************************************************************************/ |
| 236 | void mce_system_shutdown(void) |
| 237 | { |
| 238 | nvg_system_shutdown(); |
| 239 | } |
| 240 | |
| 241 | /******************************************************************************* |
| 242 | * Handler to reboot the entire system |
| 243 | ******************************************************************************/ |
| 244 | void mce_system_reboot(void) |
| 245 | { |
| 246 | nvg_system_reboot(); |
| 247 | } |
Varun Wadekar | 6718842 | 2019-03-21 08:23:05 -0700 | [diff] [blame] | 248 | |
| 249 | /******************************************************************************* |
| 250 | * Handler to clear CCPLEX->HSM correctable RAS error signal. |
| 251 | ******************************************************************************/ |
| 252 | void mce_clear_hsm_corr_status(void) |
| 253 | { |
| 254 | nvg_clear_hsm_corr_status(); |
| 255 | } |