Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __ARCH_H__ |
| 32 | #define __ARCH_H__ |
| 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | |
| 35 | /******************************************************************************* |
| 36 | * MIDR bit definitions |
| 37 | ******************************************************************************/ |
| 38 | #define MIDR_PN_MASK 0xfff |
| 39 | #define MIDR_PN_SHIFT 0x4 |
| 40 | #define MIDR_PN_AEM 0xd0f |
| 41 | #define MIDR_PN_A57 0xd07 |
| 42 | #define MIDR_PN_A53 0xd03 |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * MPIDR macros |
| 46 | ******************************************************************************/ |
| 47 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
| 48 | #define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS |
| 49 | #define MPIDR_AFFINITY_BITS 8 |
| 50 | #define MPIDR_AFFLVL_MASK 0xff |
| 51 | #define MPIDR_AFF0_SHIFT 0 |
| 52 | #define MPIDR_AFF1_SHIFT 8 |
| 53 | #define MPIDR_AFF2_SHIFT 16 |
| 54 | #define MPIDR_AFF3_SHIFT 32 |
| 55 | #define MPIDR_AFFINITY_MASK 0xff00ffffff |
| 56 | #define MPIDR_AFFLVL_SHIFT 3 |
| 57 | #define MPIDR_AFFLVL0 0 |
| 58 | #define MPIDR_AFFLVL1 1 |
| 59 | #define MPIDR_AFFLVL2 2 |
| 60 | #define MPIDR_AFFLVL3 3 |
| 61 | /* TODO: Support only the first 3 affinity levels for now */ |
| 62 | #define MPIDR_MAX_AFFLVL 2 |
| 63 | |
| 64 | /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ |
| 65 | #define FIRST_MPIDR 0 |
| 66 | |
| 67 | /******************************************************************************* |
| 68 | * Implementation defined sysreg encodings |
| 69 | ******************************************************************************/ |
| 70 | #define CPUECTLR_EL1 S3_1_C15_C2_1 |
| 71 | |
| 72 | /******************************************************************************* |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 73 | * Generic timer memory mapped registers & offsets |
| 74 | ******************************************************************************/ |
| 75 | #define CNTCR_OFF 0x000 |
| 76 | #define CNTFID_OFF 0x020 |
| 77 | |
| 78 | #define CNTCR_EN (1 << 0) |
| 79 | #define CNTCR_HDBG (1 << 1) |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 80 | #define CNTCR_FCREQ(x) ((x) << 8) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 81 | |
| 82 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | * System register bit definitions |
| 84 | ******************************************************************************/ |
| 85 | /* CLIDR definitions */ |
| 86 | #define LOUIS_SHIFT 21 |
| 87 | #define LOC_SHIFT 24 |
| 88 | #define CLIDR_FIELD_WIDTH 3 |
| 89 | |
| 90 | /* CSSELR definitions */ |
| 91 | #define LEVEL_SHIFT 1 |
| 92 | |
| 93 | /* D$ set/way op type defines */ |
| 94 | #define DCISW 0x0 |
| 95 | #define DCCISW 0x1 |
| 96 | #define DCCSW 0x2 |
| 97 | |
| 98 | /* ID_AA64PFR0_EL1 definitions */ |
| 99 | #define ID_AA64PFR0_EL0_SHIFT 0 |
| 100 | #define ID_AA64PFR0_EL1_SHIFT 4 |
| 101 | #define ID_AA64PFR0_EL2_SHIFT 8 |
| 102 | #define ID_AA64PFR0_EL3_SHIFT 12 |
| 103 | #define ID_AA64PFR0_ELX_MASK 0xf |
| 104 | |
| 105 | /* ID_PFR1_EL1 definitions */ |
| 106 | #define ID_PFR1_VIRTEXT_SHIFT 12 |
| 107 | #define ID_PFR1_VIRTEXT_MASK 0xf |
| 108 | #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ |
| 109 | & ID_PFR1_VIRTEXT_MASK) |
| 110 | |
| 111 | /* SCTLR definitions */ |
| 112 | #define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ |
| 113 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ |
| 114 | (1 << 4)) |
| 115 | |
| 116 | #define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ |
| 117 | (1 << 11)) |
| 118 | #define SCTLR_M_BIT (1 << 0) |
| 119 | #define SCTLR_A_BIT (1 << 1) |
| 120 | #define SCTLR_C_BIT (1 << 2) |
| 121 | #define SCTLR_SA_BIT (1 << 3) |
| 122 | #define SCTLR_B_BIT (1 << 7) |
| 123 | #define SCTLR_Z_BIT (1 << 11) |
| 124 | #define SCTLR_I_BIT (1 << 12) |
| 125 | #define SCTLR_WXN_BIT (1 << 19) |
| 126 | #define SCTLR_EXCEPTION_BITS (0x3 << 6) |
| 127 | #define SCTLR_EE_BIT (1 << 25) |
| 128 | |
| 129 | /* CPUECTLR definitions */ |
| 130 | #define CPUECTLR_SMP_BIT (1 << 6) |
| 131 | |
| 132 | /* CPACR_El1 definitions */ |
| 133 | #define CPACR_EL1_FPEN(x) (x << 20) |
| 134 | #define CPACR_EL1_FP_TRAP_EL0 0x1 |
| 135 | #define CPACR_EL1_FP_TRAP_ALL 0x2 |
| 136 | #define CPACR_EL1_FP_TRAP_NONE 0x3 |
| 137 | |
| 138 | /* SCR definitions */ |
| 139 | #define SCR_RES1_BITS ((1 << 4) | (1 << 5)) |
| 140 | #define SCR_TWE_BIT (1 << 13) |
| 141 | #define SCR_TWI_BIT (1 << 12) |
| 142 | #define SCR_ST_BIT (1 << 11) |
| 143 | #define SCR_RW_BIT (1 << 10) |
| 144 | #define SCR_SIF_BIT (1 << 9) |
| 145 | #define SCR_HCE_BIT (1 << 8) |
| 146 | #define SCR_SMD_BIT (1 << 7) |
| 147 | #define SCR_EA_BIT (1 << 3) |
| 148 | #define SCR_FIQ_BIT (1 << 2) |
| 149 | #define SCR_IRQ_BIT (1 << 1) |
| 150 | #define SCR_NS_BIT (1 << 0) |
| 151 | |
| 152 | /* HCR definitions */ |
| 153 | #define HCR_RW_BIT (1ull << 31) |
| 154 | #define HCR_AMO_BIT (1 << 5) |
| 155 | #define HCR_IMO_BIT (1 << 4) |
| 156 | #define HCR_FMO_BIT (1 << 3) |
| 157 | |
| 158 | /* CNTHCTL_EL2 definitions */ |
| 159 | #define EL1PCEN_BIT (1 << 1) |
| 160 | #define EL1PCTEN_BIT (1 << 0) |
| 161 | |
| 162 | /* CNTKCTL_EL1 definitions */ |
| 163 | #define EL0PTEN_BIT (1 << 9) |
| 164 | #define EL0VTEN_BIT (1 << 8) |
| 165 | #define EL0PCTEN_BIT (1 << 0) |
| 166 | #define EL0VCTEN_BIT (1 << 1) |
| 167 | |
| 168 | /* CPTR_EL3 definitions */ |
Harry Liebel | 4f60368 | 2014-01-14 18:11:48 +0000 | [diff] [blame] | 169 | #define TCPAC_BIT (1 << 31) |
| 170 | #define TTA_BIT (1 << 20) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | #define TFP_BIT (1 << 10) |
| 172 | |
| 173 | /* CPSR/SPSR definitions */ |
| 174 | #define DAIF_FIQ_BIT (1 << 0) |
| 175 | #define DAIF_IRQ_BIT (1 << 1) |
| 176 | #define DAIF_ABT_BIT (1 << 2) |
| 177 | #define DAIF_DBG_BIT (1 << 3) |
| 178 | #define PSR_DAIF_SHIFT 0x6 |
| 179 | |
| 180 | /* |
| 181 | * TCR defintions |
| 182 | */ |
| 183 | #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) |
| 184 | |
| 185 | #define TCR_T0SZ_4GB 32 |
| 186 | |
| 187 | #define TCR_RGN_INNER_NC (0x0 << 8) |
| 188 | #define TCR_RGN_INNER_WBA (0x1 << 8) |
| 189 | #define TCR_RGN_INNER_WT (0x2 << 8) |
| 190 | #define TCR_RGN_INNER_WBNA (0x3 << 8) |
| 191 | |
| 192 | #define TCR_RGN_OUTER_NC (0x0 << 10) |
| 193 | #define TCR_RGN_OUTER_WBA (0x1 << 10) |
| 194 | #define TCR_RGN_OUTER_WT (0x2 << 10) |
| 195 | #define TCR_RGN_OUTER_WBNA (0x3 << 10) |
| 196 | |
| 197 | #define TCR_SH_NON_SHAREABLE (0x0 << 12) |
| 198 | #define TCR_SH_OUTER_SHAREABLE (0x2 << 12) |
| 199 | #define TCR_SH_INNER_SHAREABLE (0x3 << 12) |
| 200 | |
| 201 | #define MODE_RW_64 0x0 |
| 202 | #define MODE_RW_32 0x1 |
| 203 | #define MODE_SP_EL0 0x0 |
| 204 | #define MODE_SP_ELX 0x1 |
| 205 | #define MODE_EL3 0x3 |
| 206 | #define MODE_EL2 0x2 |
| 207 | #define MODE_EL1 0x1 |
| 208 | #define MODE_EL0 0x0 |
| 209 | |
| 210 | #define MODE_RW_SHIFT 0x4 |
| 211 | #define MODE_EL_SHIFT 0x2 |
| 212 | #define MODE_SP_SHIFT 0x0 |
| 213 | |
| 214 | #define GET_RW(mode) ((mode >> MODE_RW_SHIFT) & 0x1) |
| 215 | #define GET_EL(mode) ((mode >> MODE_EL_SHIFT) & 0x3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 216 | #define PSR_MODE(rw, el, sp) (rw << MODE_RW_SHIFT | el << MODE_EL_SHIFT \ |
| 217 | | sp << MODE_SP_SHIFT) |
| 218 | |
| 219 | #define SPSR32_EE_BIT (1 << 9) |
| 220 | #define SPSR32_T_BIT (1 << 5) |
| 221 | |
| 222 | #define AARCH32_MODE_SVC 0x13 |
| 223 | #define AARCH32_MODE_HYP 0x1a |
| 224 | |
| 225 | /* Miscellaneous MMU related constants */ |
| 226 | #define NUM_2MB_IN_GB (1 << 9) |
| 227 | #define NUM_4K_IN_2MB (1 << 9) |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 228 | #define NUM_GB_IN_4GB (1 << 2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 229 | |
| 230 | #define TWO_MB_SHIFT 21 |
| 231 | #define ONE_GB_SHIFT 30 |
| 232 | #define FOUR_KB_SHIFT 12 |
| 233 | |
| 234 | #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) |
| 235 | #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) |
| 236 | #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) |
| 237 | |
| 238 | #define INVALID_DESC 0x0 |
| 239 | #define BLOCK_DESC 0x1 |
| 240 | #define TABLE_DESC 0x3 |
| 241 | |
| 242 | #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT |
| 243 | #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT |
| 244 | #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT |
| 245 | |
| 246 | #define LEVEL1 1 |
| 247 | #define LEVEL2 2 |
| 248 | #define LEVEL3 3 |
| 249 | |
| 250 | #define XN (1ull << 2) |
| 251 | #define PXN (1ull << 1) |
| 252 | #define CONT_HINT (1ull << 0) |
| 253 | |
| 254 | #define UPPER_ATTRS(x) (x & 0x7) << 52 |
| 255 | #define NON_GLOBAL (1 << 9) |
| 256 | #define ACCESS_FLAG (1 << 8) |
| 257 | #define NSH (0x0 << 6) |
| 258 | #define OSH (0x2 << 6) |
| 259 | #define ISH (0x3 << 6) |
| 260 | |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 261 | #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT |
| 262 | #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) |
| 263 | #define PAGE_SIZE_MASK (PAGE_SIZE - 1) |
| 264 | #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) |
| 265 | |
| 266 | #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ |
| 267 | #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) |
| 268 | |
| 269 | #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT |
| 270 | #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) |
| 271 | |
| 272 | /* Values for number of entries in each MMU translation table */ |
| 273 | #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) |
| 274 | #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) |
| 275 | #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) |
| 276 | |
| 277 | /* Values to convert a memory address to an index into a translation table */ |
| 278 | #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT |
| 279 | #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) |
| 280 | #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 281 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 282 | /* |
| 283 | * AP[1] bit is ignored by hardware and is |
| 284 | * treated as if it is One in EL2/EL3 |
| 285 | */ |
| 286 | #define AP_RO (0x1 << 5) |
| 287 | #define AP_RW (0x0 << 5) |
| 288 | |
| 289 | #define NS (0x1 << 3) |
| 290 | #define ATTR_SO_INDEX 0x2 |
| 291 | #define ATTR_DEVICE_INDEX 0x1 |
| 292 | #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 |
| 293 | #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) |
| 294 | #define ATTR_SO (0x0) |
| 295 | #define ATTR_DEVICE (0x4) |
| 296 | #define ATTR_IWBWA_OWBWA_NTR (0xff) |
| 297 | #define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) |
| 298 | |
| 299 | /* Exception Syndrome register bits and bobs */ |
| 300 | #define ESR_EC_SHIFT 26 |
| 301 | #define ESR_EC_MASK 0x3f |
| 302 | #define ESR_EC_LENGTH 6 |
| 303 | #define EC_UNKNOWN 0x0 |
| 304 | #define EC_WFE_WFI 0x1 |
| 305 | #define EC_AARCH32_CP15_MRC_MCR 0x3 |
| 306 | #define EC_AARCH32_CP15_MRRC_MCRR 0x4 |
| 307 | #define EC_AARCH32_CP14_MRC_MCR 0x5 |
| 308 | #define EC_AARCH32_CP14_LDC_STC 0x6 |
| 309 | #define EC_FP_SIMD 0x7 |
| 310 | #define EC_AARCH32_CP10_MRC 0x8 |
| 311 | #define EC_AARCH32_CP14_MRRC_MCRR 0xc |
| 312 | #define EC_ILLEGAL 0xe |
| 313 | #define EC_AARCH32_SVC 0x11 |
| 314 | #define EC_AARCH32_HVC 0x12 |
| 315 | #define EC_AARCH32_SMC 0x13 |
| 316 | #define EC_AARCH64_SVC 0x15 |
| 317 | #define EC_AARCH64_HVC 0x16 |
| 318 | #define EC_AARCH64_SMC 0x17 |
| 319 | #define EC_AARCH64_SYS 0x18 |
| 320 | #define EC_IABORT_LOWER_EL 0x20 |
| 321 | #define EC_IABORT_CUR_EL 0x21 |
| 322 | #define EC_PC_ALIGN 0x22 |
| 323 | #define EC_DABORT_LOWER_EL 0x24 |
| 324 | #define EC_DABORT_CUR_EL 0x25 |
| 325 | #define EC_SP_ALIGN 0x26 |
| 326 | #define EC_AARCH32_FP 0x28 |
| 327 | #define EC_AARCH64_FP 0x2c |
| 328 | #define EC_SERROR 0x2f |
| 329 | |
| 330 | #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK |
| 331 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 332 | #endif /* __ARCH_H__ */ |