blob: 376da4947fcbd2af5ab6c7d530c64e934f1314b2 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Achin Gupta4f6ad662013-10-25 09:08:21 +010034 .globl read_vbar_el1
35 .globl read_vbar_el2
36 .globl read_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 .globl write_vbar_el1
38 .globl write_vbar_el2
39 .globl write_vbar_el3
40
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 .globl read_sctlr_el1
42 .globl read_sctlr_el2
43 .globl read_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010044 .globl write_sctlr_el1
45 .globl write_sctlr_el2
46 .globl write_sctlr_el3
47
Achin Gupta4f6ad662013-10-25 09:08:21 +010048 .globl read_actlr_el1
49 .globl read_actlr_el2
50 .globl read_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 .globl write_actlr_el1
52 .globl write_actlr_el2
53 .globl write_actlr_el3
54
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 .globl read_esr_el1
56 .globl read_esr_el2
57 .globl read_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010058 .globl write_esr_el1
59 .globl write_esr_el2
60 .globl write_esr_el3
61
Achin Gupta4f6ad662013-10-25 09:08:21 +010062 .globl read_afsr0_el1
63 .globl read_afsr0_el2
64 .globl read_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010065 .globl write_afsr0_el1
66 .globl write_afsr0_el2
67 .globl write_afsr0_el3
68
Achin Gupta4f6ad662013-10-25 09:08:21 +010069 .globl read_afsr1_el1
70 .globl read_afsr1_el2
71 .globl read_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010072 .globl write_afsr1_el1
73 .globl write_afsr1_el2
74 .globl write_afsr1_el3
75
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 .globl read_far_el1
77 .globl read_far_el2
78 .globl read_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 .globl write_far_el1
80 .globl write_far_el2
81 .globl write_far_el3
82
Achin Gupta4f6ad662013-10-25 09:08:21 +010083 .globl read_mair_el1
84 .globl read_mair_el2
85 .globl read_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 .globl write_mair_el1
87 .globl write_mair_el2
88 .globl write_mair_el3
89
Achin Gupta4f6ad662013-10-25 09:08:21 +010090 .globl read_amair_el1
91 .globl read_amair_el2
92 .globl read_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 .globl write_amair_el1
94 .globl write_amair_el2
95 .globl write_amair_el3
96
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 .globl read_rvbar_el1
98 .globl read_rvbar_el2
99 .globl read_rvbar_el3
100
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 .globl read_rmr_el1
102 .globl read_rmr_el2
103 .globl read_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 .globl write_rmr_el1
105 .globl write_rmr_el2
106 .globl write_rmr_el3
107
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 .globl read_tcr_el1
109 .globl read_tcr_el2
110 .globl read_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 .globl write_tcr_el1
112 .globl write_tcr_el2
113 .globl write_tcr_el3
114
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 .globl read_cptr_el2
116 .globl read_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117 .globl write_cptr_el2
118 .globl write_cptr_el3
119
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120 .globl read_ttbr0_el1
121 .globl read_ttbr0_el2
122 .globl read_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 .globl write_ttbr0_el1
124 .globl write_ttbr0_el2
125 .globl write_ttbr0_el3
126
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 .globl read_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 .globl write_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129
130 .globl read_cpacr
131 .globl write_cpacr
132
133 .globl read_cntfrq
134 .globl write_cntfrq
135
136 .globl read_cpuectlr
137 .globl write_cpuectlr
138
139 .globl read_cnthctl_el2
140 .globl write_cnthctl_el2
141
142 .globl read_cntfrq_el0
143 .globl write_cntfrq_el0
144
145 .globl read_scr
146 .globl write_scr
147
148 .globl read_hcr
149 .globl write_hcr
150
151 .globl read_midr
152 .globl read_mpidr
153
154 .globl read_current_el
155 .globl read_id_pfr1_el1
156 .globl read_id_aa64pfr0_el1
157
158#if SUPPORT_VFP
159 .globl enable_vfp
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160#endif
161
162
Andrew Thoelke38bde412014-03-18 13:46:55 +0000163func read_current_el
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164 mrs x0, CurrentEl
165 ret
166
167
Andrew Thoelke38bde412014-03-18 13:46:55 +0000168func read_id_pfr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169 mrs x0, id_pfr1_el1
170 ret
171
172
Andrew Thoelke38bde412014-03-18 13:46:55 +0000173func read_id_aa64pfr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 mrs x0, id_aa64pfr0_el1
175 ret
176
177
178 /* -----------------------------------------------------
179 * VBAR accessors
180 * -----------------------------------------------------
181 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000182func read_vbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183 mrs x0, vbar_el1
184 ret
185
186
Andrew Thoelke38bde412014-03-18 13:46:55 +0000187func read_vbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 mrs x0, vbar_el2
189 ret
190
191
Andrew Thoelke38bde412014-03-18 13:46:55 +0000192func read_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 mrs x0, vbar_el3
194 ret
195
196
Andrew Thoelke38bde412014-03-18 13:46:55 +0000197func write_vbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198 msr vbar_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199 ret
200
201
Andrew Thoelke38bde412014-03-18 13:46:55 +0000202func write_vbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 msr vbar_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204 ret
205
206
Andrew Thoelke38bde412014-03-18 13:46:55 +0000207func write_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208 msr vbar_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209 ret
210
211
212 /* -----------------------------------------------------
213 * AFSR0 accessors
214 * -----------------------------------------------------
215 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000216func read_afsr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 mrs x0, afsr0_el1
218 ret
219
220
Andrew Thoelke38bde412014-03-18 13:46:55 +0000221func read_afsr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 mrs x0, afsr0_el2
223 ret
224
225
Andrew Thoelke38bde412014-03-18 13:46:55 +0000226func read_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227 mrs x0, afsr0_el3
228 ret
229
230
Andrew Thoelke38bde412014-03-18 13:46:55 +0000231func write_afsr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232 msr afsr0_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 ret
234
235
Andrew Thoelke38bde412014-03-18 13:46:55 +0000236func write_afsr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100237 msr afsr0_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238 ret
239
240
Andrew Thoelke38bde412014-03-18 13:46:55 +0000241func write_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242 msr afsr0_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243 ret
244
245
246 /* -----------------------------------------------------
247 * FAR accessors
248 * -----------------------------------------------------
249 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000250func read_far_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251 mrs x0, far_el1
252 ret
253
254
Andrew Thoelke38bde412014-03-18 13:46:55 +0000255func read_far_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256 mrs x0, far_el2
257 ret
258
259
Andrew Thoelke38bde412014-03-18 13:46:55 +0000260func read_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100261 mrs x0, far_el3
262 ret
263
264
Andrew Thoelke38bde412014-03-18 13:46:55 +0000265func write_far_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266 msr far_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267 ret
268
269
Andrew Thoelke38bde412014-03-18 13:46:55 +0000270func write_far_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271 msr far_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272 ret
273
274
Andrew Thoelke38bde412014-03-18 13:46:55 +0000275func write_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276 msr far_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277 ret
278
279
280 /* -----------------------------------------------------
281 * MAIR accessors
282 * -----------------------------------------------------
283 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000284func read_mair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285 mrs x0, mair_el1
286 ret
287
288
Andrew Thoelke38bde412014-03-18 13:46:55 +0000289func read_mair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290 mrs x0, mair_el2
291 ret
292
293
Andrew Thoelke38bde412014-03-18 13:46:55 +0000294func read_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295 mrs x0, mair_el3
296 ret
297
298
Andrew Thoelke38bde412014-03-18 13:46:55 +0000299func write_mair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100300 msr mair_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100301 ret
302
303
Andrew Thoelke38bde412014-03-18 13:46:55 +0000304func write_mair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305 msr mair_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100306 ret
307
308
Andrew Thoelke38bde412014-03-18 13:46:55 +0000309func write_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310 msr mair_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311 ret
312
313
314 /* -----------------------------------------------------
315 * AMAIR accessors
316 * -----------------------------------------------------
317 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000318func read_amair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100319 mrs x0, amair_el1
320 ret
321
322
Andrew Thoelke38bde412014-03-18 13:46:55 +0000323func read_amair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324 mrs x0, amair_el2
325 ret
326
327
Andrew Thoelke38bde412014-03-18 13:46:55 +0000328func read_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100329 mrs x0, amair_el3
330 ret
331
332
Andrew Thoelke38bde412014-03-18 13:46:55 +0000333func write_amair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100334 msr amair_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100335 ret
336
337
Andrew Thoelke38bde412014-03-18 13:46:55 +0000338func write_amair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100339 msr amair_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100340 ret
341
342
Andrew Thoelke38bde412014-03-18 13:46:55 +0000343func write_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100344 msr amair_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100345 ret
346
347
348 /* -----------------------------------------------------
349 * RVBAR accessors
350 * -----------------------------------------------------
351 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000352func read_rvbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353 mrs x0, rvbar_el1
354 ret
355
356
Andrew Thoelke38bde412014-03-18 13:46:55 +0000357func read_rvbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100358 mrs x0, rvbar_el2
359 ret
360
361
Andrew Thoelke38bde412014-03-18 13:46:55 +0000362func read_rvbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100363 mrs x0, rvbar_el3
364 ret
365
366
367 /* -----------------------------------------------------
368 * RMR accessors
369 * -----------------------------------------------------
370 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000371func read_rmr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100372 mrs x0, rmr_el1
373 ret
374
375
Andrew Thoelke38bde412014-03-18 13:46:55 +0000376func read_rmr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100377 mrs x0, rmr_el2
378 ret
379
380
Andrew Thoelke38bde412014-03-18 13:46:55 +0000381func read_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100382 mrs x0, rmr_el3
383 ret
384
385
Andrew Thoelke38bde412014-03-18 13:46:55 +0000386func write_rmr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100387 msr rmr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100388 ret
389
390
Andrew Thoelke38bde412014-03-18 13:46:55 +0000391func write_rmr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100392 msr rmr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100393 ret
394
395
Andrew Thoelke38bde412014-03-18 13:46:55 +0000396func write_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397 msr rmr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100398 ret
399
400
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401 /* -----------------------------------------------------
402 * AFSR1 accessors
403 * -----------------------------------------------------
404 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000405func read_afsr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100406 mrs x0, afsr1_el1
407 ret
408
409
Andrew Thoelke38bde412014-03-18 13:46:55 +0000410func read_afsr1_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100411 mrs x0, afsr1_el2
412 ret
413
414
Andrew Thoelke38bde412014-03-18 13:46:55 +0000415func read_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100416 mrs x0, afsr1_el3
417 ret
418
419
Andrew Thoelke38bde412014-03-18 13:46:55 +0000420func write_afsr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100421 msr afsr1_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100422 ret
423
424
Andrew Thoelke38bde412014-03-18 13:46:55 +0000425func write_afsr1_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100426 msr afsr1_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100427 ret
428
429
Andrew Thoelke38bde412014-03-18 13:46:55 +0000430func write_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100431 msr afsr1_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100432 ret
433
434
435 /* -----------------------------------------------------
436 * SCTLR accessors
437 * -----------------------------------------------------
438 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000439func read_sctlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100440 mrs x0, sctlr_el1
441 ret
442
443
Andrew Thoelke38bde412014-03-18 13:46:55 +0000444func read_sctlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100445 mrs x0, sctlr_el2
446 ret
447
448
Andrew Thoelke38bde412014-03-18 13:46:55 +0000449func read_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100450 mrs x0, sctlr_el3
451 ret
452
453
Andrew Thoelke38bde412014-03-18 13:46:55 +0000454func write_sctlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100455 msr sctlr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100456 ret
457
458
Andrew Thoelke38bde412014-03-18 13:46:55 +0000459func write_sctlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100460 msr sctlr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100461 ret
462
463
Andrew Thoelke38bde412014-03-18 13:46:55 +0000464func write_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100465 msr sctlr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100466 ret
467
468
469 /* -----------------------------------------------------
470 * ACTLR accessors
471 * -----------------------------------------------------
472 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000473func read_actlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100474 mrs x0, actlr_el1
475 ret
476
477
Andrew Thoelke38bde412014-03-18 13:46:55 +0000478func read_actlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100479 mrs x0, actlr_el2
480 ret
481
482
Andrew Thoelke38bde412014-03-18 13:46:55 +0000483func read_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100484 mrs x0, actlr_el3
485 ret
486
487
Andrew Thoelke38bde412014-03-18 13:46:55 +0000488func write_actlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100489 msr actlr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100490 ret
491
492
Andrew Thoelke38bde412014-03-18 13:46:55 +0000493func write_actlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100494 msr actlr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100495 ret
496
497
Andrew Thoelke38bde412014-03-18 13:46:55 +0000498func write_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100499 msr actlr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100500 ret
501
502
503 /* -----------------------------------------------------
504 * ESR accessors
505 * -----------------------------------------------------
506 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000507func read_esr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100508 mrs x0, esr_el1
509 ret
510
511
Andrew Thoelke38bde412014-03-18 13:46:55 +0000512func read_esr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100513 mrs x0, esr_el2
514 ret
515
516
Andrew Thoelke38bde412014-03-18 13:46:55 +0000517func read_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100518 mrs x0, esr_el3
519 ret
520
521
Andrew Thoelke38bde412014-03-18 13:46:55 +0000522func write_esr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100523 msr esr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100524 ret
525
526
Andrew Thoelke38bde412014-03-18 13:46:55 +0000527func write_esr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100528 msr esr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100529 ret
530
531
Andrew Thoelke38bde412014-03-18 13:46:55 +0000532func write_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100533 msr esr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100534 ret
535
536
537 /* -----------------------------------------------------
538 * TCR accessors
539 * -----------------------------------------------------
540 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000541func read_tcr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100542 mrs x0, tcr_el1
543 ret
544
545
Andrew Thoelke38bde412014-03-18 13:46:55 +0000546func read_tcr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100547 mrs x0, tcr_el2
548 ret
549
550
Andrew Thoelke38bde412014-03-18 13:46:55 +0000551func read_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100552 mrs x0, tcr_el3
553 ret
554
Achin Gupta4f6ad662013-10-25 09:08:21 +0100555
Andrew Thoelke38bde412014-03-18 13:46:55 +0000556func write_tcr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100557 msr tcr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100558 ret
559
560
Andrew Thoelke38bde412014-03-18 13:46:55 +0000561func write_tcr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100562 msr tcr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100563 ret
564
565
Andrew Thoelke38bde412014-03-18 13:46:55 +0000566func write_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100567 msr tcr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100568 ret
569
570
571 /* -----------------------------------------------------
572 * CPTR accessors
573 * -----------------------------------------------------
574 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000575func read_cptr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100576 mrs x0, cptr_el2
577 ret
578
579
Andrew Thoelke38bde412014-03-18 13:46:55 +0000580func read_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100581 mrs x0, cptr_el3
582 ret
583
Achin Gupta4f6ad662013-10-25 09:08:21 +0100584
Andrew Thoelke38bde412014-03-18 13:46:55 +0000585func write_cptr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100586 msr cptr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100587 ret
588
589
Andrew Thoelke38bde412014-03-18 13:46:55 +0000590func write_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100591 msr cptr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100592 ret
593
594
595 /* -----------------------------------------------------
596 * TTBR0 accessors
597 * -----------------------------------------------------
598 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000599func read_ttbr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100600 mrs x0, ttbr0_el1
601 ret
602
603
Andrew Thoelke38bde412014-03-18 13:46:55 +0000604func read_ttbr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100605 mrs x0, ttbr0_el2
606 ret
607
608
Andrew Thoelke38bde412014-03-18 13:46:55 +0000609func read_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100610 mrs x0, ttbr0_el3
611 ret
612
613
Andrew Thoelke38bde412014-03-18 13:46:55 +0000614func write_ttbr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100615 msr ttbr0_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100616 ret
617
618
Andrew Thoelke38bde412014-03-18 13:46:55 +0000619func write_ttbr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100620 msr ttbr0_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100621 ret
622
623
Andrew Thoelke38bde412014-03-18 13:46:55 +0000624func write_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100625 msr ttbr0_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100626 ret
627
628
629 /* -----------------------------------------------------
630 * TTBR1 accessors
631 * -----------------------------------------------------
632 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000633func read_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100634 mrs x0, ttbr1_el1
635 ret
636
637
Andrew Thoelke38bde412014-03-18 13:46:55 +0000638func write_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100639 msr ttbr1_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100640 ret
641
642
Andrew Thoelke38bde412014-03-18 13:46:55 +0000643func read_hcr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100644 mrs x0, hcr_el2
645 ret
646
647
Andrew Thoelke38bde412014-03-18 13:46:55 +0000648func write_hcr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100649 msr hcr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100650 ret
651
652
Andrew Thoelke38bde412014-03-18 13:46:55 +0000653func read_cpacr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100654 mrs x0, cpacr_el1
655 ret
656
657
Andrew Thoelke38bde412014-03-18 13:46:55 +0000658func write_cpacr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100659 msr cpacr_el1, x0
660 ret
661
662
Andrew Thoelke38bde412014-03-18 13:46:55 +0000663func read_cntfrq_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100664 mrs x0, cntfrq_el0
665 ret
666
667
Andrew Thoelke38bde412014-03-18 13:46:55 +0000668func write_cntfrq_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100669 msr cntfrq_el0, x0
670 ret
671
672
Andrew Thoelke38bde412014-03-18 13:46:55 +0000673func read_cpuectlr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100674 mrs x0, CPUECTLR_EL1
675 ret
676
677
Andrew Thoelke38bde412014-03-18 13:46:55 +0000678func write_cpuectlr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100679 msr CPUECTLR_EL1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100680 ret
681
682
Andrew Thoelke38bde412014-03-18 13:46:55 +0000683func read_cnthctl_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100684 mrs x0, cnthctl_el2
685 ret
686
687
Andrew Thoelke38bde412014-03-18 13:46:55 +0000688func write_cnthctl_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100689 msr cnthctl_el2, x0
690 ret
691
692
Andrew Thoelke38bde412014-03-18 13:46:55 +0000693func read_cntfrq
Achin Gupta4f6ad662013-10-25 09:08:21 +0100694 mrs x0, cntfrq_el0
695 ret
696
697
Andrew Thoelke38bde412014-03-18 13:46:55 +0000698func write_cntfrq
Achin Gupta4f6ad662013-10-25 09:08:21 +0100699 msr cntfrq_el0, x0
700 ret
701
702
Andrew Thoelke38bde412014-03-18 13:46:55 +0000703func write_scr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100704 msr scr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100705 ret
706
707
Andrew Thoelke38bde412014-03-18 13:46:55 +0000708func read_scr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100709 mrs x0, scr_el3
710 ret
711
712
Andrew Thoelke38bde412014-03-18 13:46:55 +0000713func read_midr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100714 mrs x0, midr_el1
715 ret
716
717
Andrew Thoelke38bde412014-03-18 13:46:55 +0000718func read_mpidr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100719 mrs x0, mpidr_el1
720 ret
721
722
723#if SUPPORT_VFP
Andrew Thoelke38bde412014-03-18 13:46:55 +0000724func enable_vfp
Achin Gupta4f6ad662013-10-25 09:08:21 +0100725 mrs x0, cpacr_el1
726 orr x0, x0, #CPACR_VFP_BITS
727 msr cpacr_el1, x0
728 mrs x0, cptr_el3
729 mov x1, #AARCH64_CPTR_TFP
730 bic x0, x0, x1
731 msr cptr_el3, x0
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100732 isb
Achin Gupta4f6ad662013-10-25 09:08:21 +0100733 ret
734
Achin Gupta4f6ad662013-10-25 09:08:21 +0100735#endif