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git01.mediatek.com / filogic / atf / 6b88b65895a9477165e11d330131f5af93f57227 / . / plat / marvell / a8k / a80x0 / board / phy-porting-layer.h
blob: 38497fb5367ef846b4d1e00f861b8a8591c1dea8 [file] [log] [blame]
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef PHY_PORTING_LAYER_H
9#define PHY_PORTING_LAYER_H
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200[diff] [blame]10
11#define MAX_LANE_NR 6
12
13static const struct xfi_params
14 xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
15 /* AP0 */
16 {
17 /* CP 0 */
18 {
19 { 0 }, /* Comphy0 */
20 { 0 }, /* Comphy1 */
21 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
22 .align90 = 0x5f,
23 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
24 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
25 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
26 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
27 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
28 .valid = 0x1 }, /* Comphy2 */
29 { 0 }, /* Comphy3 */
30 { 0 }, /* Comphy4 */
31 { 0 }, /* Comphy5 */
32 },
33
34 /* CP 1 */
35 {
36 { 0 }, /* Comphy0 */
37 { 0 }, /* Comphy1 */
38 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
39 .align90 = 0x5f,
40 .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
41 .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
42 .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
43 .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
44 .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
45 .valid = 0x1 }, /* Comphy2 */
46 { 0 }, /* Comphy3 */
47 { 0 }, /* Comphy4 */
48 { 0 }, /* Comphy5 */
49 },
50 },
51};
52
53static const struct sata_params
54 sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
55 /* AP0 */
56 {
57 /* CP 0 */
58 {
59 { 0 }, /* Comphy0 */
60 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
61 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
62 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
63 .g3_emph_en = 0x1,
64 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
65 .g3_tx_amp_adj = 0x1,
66 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
67 .g3_tx_emph_en = 0x0,
68 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
69 .g3_tx_emph = 0x1,
70 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
71 .g3_ffe_cap_sel = 0xf,
72 .align90 = 0x61,
73 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
74 .g3_rx_selmuff = 0x3,
75 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
76 .g3_rx_selmufi = 0x3,
77 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
78 .g3_rx_selmupf = 0x2,
79 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
80 .g3_rx_selmupi = 0x2,
81 .valid = 0x1
82 }, /* Comphy1 */
83 { 0 }, /* Comphy2 */
84 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
85 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
86 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
87 .g3_emph_en = 0x1,
88 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
89 .g3_tx_amp_adj = 0x1,
90 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
91 .g3_tx_emph_en = 0x0,
92 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
93 .g3_tx_emph = 0x1,
94 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
95 .g3_ffe_cap_sel = 0xf,
96 .align90 = 0x61,
97 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
98 .g3_rx_selmuff = 0x3,
99 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
100 .g3_rx_selmufi = 0x3,
101 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
102 .g3_rx_selmupf = 0x2,
103 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
104 .g3_rx_selmupi = 0x2,
105 .valid = 0x1
106 }, /* Comphy3 */
107 { 0 }, /* Comphy4 */
108 { 0 }, /* Comphy5 */
109 },
110
111 /* CP 1 */
112 {
113 { 0 }, /* Comphy0 */
114 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
115 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
116 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
117 .g3_emph_en = 0x1,
118 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
119 .g3_tx_amp_adj = 0x1,
120 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
121 .g3_tx_emph_en = 0x0,
122 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
123 .g3_tx_emph = 0x1,
124 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
125 .g3_ffe_cap_sel = 0xf,
126 .align90 = 0x61,
127 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
128 .g3_rx_selmuff = 0x3,
129 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
130 .g3_rx_selmufi = 0x3,
131 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
132 .g3_rx_selmupf = 0x2,
133 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
134 .g3_rx_selmupi = 0x2,
135 .valid = 0x1
136 }, /* Comphy1 */
137 { 0 }, /* Comphy2 */
138 { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
139 .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
140 .g1_emph_en = 0x1, .g2_emph_en = 0x1,
141 .g3_emph_en = 0x1,
142 .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
143 .g3_tx_amp_adj = 0x1,
144 .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
145 .g3_tx_emph_en = 0x0,
146 .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
147 .g3_tx_emph = 0x1,
148 .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
149 .g3_ffe_cap_sel = 0xf,
150 .align90 = 0x61,
151 .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
152 .g3_rx_selmuff = 0x3,
153 .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
154 .g3_rx_selmufi = 0x3,
155 .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
156 .g3_rx_selmupf = 0x2,
157 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
158 .g3_rx_selmupi = 0x2,
159 .valid = 0x1
160 }, /* Comphy3 */
161 { 0 }, /* Comphy4 */
162 { 0 }, /* Comphy5 */
163
164 },
165 },
166};
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]167#endif /* PHY_PORTING_LAYER_H */