blob: 3c1a9e5c8a20d9b831966f4d2a8d165ca109a572 [file] [log] [blame]
Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
35#include "../zynqmp_def.h"
36
37/*******************************************************************************
38 * Generic platform constants
39 ******************************************************************************/
40
41/* Size of cacheable stacks */
42#define PLATFORM_STACK_SIZE 0x440
43
44#define PLATFORM_CORE_COUNT 4
45#define PLAT_NUM_POWER_DOMAINS 5
46#define PLAT_MAX_PWR_LVL 1
47#define PLAT_MAX_RET_STATE 1
48#define PLAT_MAX_OFF_STATE 2
49
50/*******************************************************************************
51 * BL31 specific defines.
52 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080053/*
54 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
55 * present). BL31_BASE is calculated using the current BL31 debug size plus a
56 * little space for growth.
57 */
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070058#ifndef ZYNQMP_ATF_MEM_BASE
Soren Brinkmann802ba1d2016-07-15 06:23:37 -070059# define BL31_BASE 0xfffea000
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070060# define BL31_LIMIT 0xffffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080061#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070062# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
63# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
64# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
65# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
66# endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080067#endif
68
69/*******************************************************************************
70 * BL32 specific defines.
71 ******************************************************************************/
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070072#ifndef ZYNQMP_BL32_MEM_BASE
73# define BL32_BASE 0x60000000
74# define BL32_LIMIT 0x7fffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080075#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070076# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
77# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080078#endif
79
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070080/*******************************************************************************
81 * BL33 specific defines.
82 ******************************************************************************/
83#ifndef PRELOADED_BL33_BASE
84# define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000
85#else
86# define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
87#endif
88
89/*******************************************************************************
90 * TSP specific defines.
91 ******************************************************************************/
92#define TSP_SEC_MEM_BASE BL32_BASE
93#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
94
95/* ID of the secure physical generic timer interrupt used by the TSP */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080096#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
97
98/*******************************************************************************
99 * Platform specific page table and MMU setup constants
100 ******************************************************************************/
101#define ADDR_SPACE_SIZE (1ull << 32)
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700102#define MAX_MMAP_REGIONS 7
Soren Brinkmann7ac746c2016-07-25 10:33:53 -0700103#define MAX_XLAT_TABLES 5
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800104
105#define CACHE_WRITEBACK_SHIFT 6
106#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
107
108#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
109#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
110/*
111 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
112 * terminology. On a GICv2 system or mode, the lists will be merged and treated
113 * as Group 0 interrupts.
114 */
115#define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
116 IRQ_SEC_IPI_APU, \
117 ARM_IRQ_SEC_SGI_0, \
118 ARM_IRQ_SEC_SGI_1, \
119 ARM_IRQ_SEC_SGI_2, \
120 ARM_IRQ_SEC_SGI_3, \
121 ARM_IRQ_SEC_SGI_4, \
122 ARM_IRQ_SEC_SGI_5, \
123 ARM_IRQ_SEC_SGI_6, \
124 ARM_IRQ_SEC_SGI_7
125
126#define PLAT_ARM_G0_IRQS
127
128#endif /* __PLATFORM_DEF_H__ */