| Sumit Garg | 3817202 | 2018-06-15 13:48:11 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | .global sq_calc_core_pos |
| 13 | .global plat_my_core_pos |
| 14 | .global platform_mem_init |
| 15 | .global plat_is_my_cpu_primary |
| 16 | .global plat_secondary_cold_boot_setup |
| Sumit Garg | 84711f9 | 2018-06-15 14:34:42 +0530 | [diff] [blame] | 17 | .global plat_crash_console_init |
| 18 | .global plat_crash_console_putc |
| 19 | .global plat_crash_console_flush |
| Sumit Garg | 3817202 | 2018-06-15 13:48:11 +0530 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * unsigned int sq_calc_core_pos(u_register_t mpidr) |
| 23 | * core_pos = (cluster_id * max_cpus_per_cluster) + core_id |
| 24 | */ |
| 25 | func sq_calc_core_pos |
| 26 | and x1, x0, #MPIDR_CPU_MASK |
| 27 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 28 | add x0, x1, x0, lsr #7 |
| 29 | ret |
| 30 | endfunc sq_calc_core_pos |
| 31 | |
| 32 | func plat_my_core_pos |
| 33 | mrs x0, mpidr_el1 |
| 34 | b sq_calc_core_pos |
| 35 | endfunc plat_my_core_pos |
| 36 | |
| 37 | func platform_mem_init |
| 38 | ret |
| 39 | endfunc platform_mem_init |
| 40 | |
| 41 | /* |
| 42 | * Secondary CPUs are placed in a holding pen, waiting for their mailbox |
| 43 | * to be populated. Note that all CPUs share the same mailbox ; therefore, |
| 44 | * populating it will release all CPUs from their holding pen. If |
| 45 | * finer-grained control is needed then this should be handled in the |
| 46 | * code that secondary CPUs jump to. |
| 47 | */ |
| 48 | func plat_secondary_cold_boot_setup |
| 49 | ldr x0, sq_sec_entrypoint |
| 50 | |
| 51 | /* Wait until the mailbox gets populated */ |
| 52 | poll_mailbox: |
| 53 | cbz x0, 1f |
| 54 | br x0 |
| 55 | 1: |
| 56 | wfe |
| 57 | b poll_mailbox |
| 58 | endfunc plat_secondary_cold_boot_setup |
| 59 | |
| 60 | /* |
| 61 | * Find out whether the current cpu is the primary |
| 62 | * cpu (applicable only after a cold boot) |
| 63 | */ |
| 64 | func plat_is_my_cpu_primary |
| 65 | mov x9, x30 |
| 66 | bl plat_my_core_pos |
| 67 | ldr x1, =SQ_BOOT_CFG_ADDR |
| 68 | ldr x1, [x1] |
| 69 | ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ |
| 70 | #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH |
| 71 | cmp x0, x1 |
| 72 | cset w0, eq |
| 73 | ret x9 |
| 74 | endfunc plat_is_my_cpu_primary |
| Sumit Garg | 84711f9 | 2018-06-15 14:34:42 +0530 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * int plat_crash_console_init(void) |
| 78 | * Function to initialize the crash console |
| 79 | * without a C Runtime to print crash report. |
| 80 | * Clobber list : x0, x1, x2 |
| 81 | */ |
| 82 | func plat_crash_console_init |
| 83 | mov_imm x0, PLAT_SQ_BOOT_UART_BASE |
| 84 | mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ |
| 85 | mov_imm x2, SQ_CONSOLE_BAUDRATE |
| 86 | b console_pl011_core_init |
| 87 | endfunc plat_crash_console_init |
| 88 | |
| 89 | /* |
| 90 | * int plat_crash_console_putc(int c) |
| 91 | * Function to print a character on the crash |
| 92 | * console without a C Runtime. |
| 93 | * Clobber list : x1, x2 |
| 94 | */ |
| 95 | func plat_crash_console_putc |
| 96 | mov_imm x1, PLAT_SQ_BOOT_UART_BASE |
| 97 | b console_pl011_core_putc |
| 98 | endfunc plat_crash_console_putc |
| 99 | |
| 100 | /* |
| 101 | * int plat_crash_console_flush(int c) |
| 102 | * Function to force a write of all buffered |
| 103 | * data that hasn't been output. |
| 104 | * Out : return -1 on error else return 0. |
| 105 | * Clobber list : x0, x1 |
| 106 | */ |
| 107 | func plat_crash_console_flush |
| 108 | mov_imm x0, PLAT_SQ_BOOT_UART_BASE |
| 109 | b console_pl011_core_flush |
| 110 | endfunc plat_crash_console_flush |